From patchwork Fri Dec 21 14:33:20 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 1903241 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id 890A3DF25A for ; Fri, 21 Dec 2012 14:37:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7695CE676E for ; Fri, 21 Dec 2012 06:37:44 -0800 (PST) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from fireflyinternet.com (server109-228-6-235.live-servers.net [109.228.6.235]) by gabe.freedesktop.org (Postfix) with ESMTP id 77362E630D for ; Fri, 21 Dec 2012 06:36:47 -0800 (PST) X-Default-Received-SPF: pass (skip=forwardok (res=PASS)) x-ip-name=78.156.73.22; Received: from arrandale.alporthouse.com (unverified [78.156.73.22]) by fireflyinternet.com (Firefly Internet (M1)) with ESMTP id 126580687-1500050 for multiple; Fri, 21 Dec 2012 14:36:36 +0000 From: Chris Wilson To: Linus Torvalds Subject: [PATCH] uxa: Align tiled surface size to an number of tiled rows Date: Fri, 21 Dec 2012 14:33:20 +0000 Message-Id: <1356100400-15882-1-git-send-email-chris@chris-wilson.co.uk> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: References: X-Originating-IP: 78.156.73.22 Cc: dri-devel@lists.freedesktop.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org Errors-To: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org Align surface sizes to an even number of tile rows to cater for sampler prefetch, as shown by enabling GPU invalid PTE detection (i.e. clearing the valid bit of the PTE). --- We are investigating bug https://bugs.freedesktop.org/show_bug.cgi?id=55984 where the only lead so far is the ordering of eviction under memory pressure. This patch seems promising because the GPU is detecting that we are accessing invalid pages beyond the end of our allocations (and so the eviction may lead us to randomly read the scratch PTE and randomly hang the GPU), however the only bug that I have seen with such a tell-tale error state is https://bugzilla.redhat.com/show_bug.cgi?id=877461 -Chris --- src/intel_uxa.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel_uxa.c b/src/intel_uxa.c index f5ac0a6..2f14173 100644 --- a/src/intel_uxa.c +++ b/src/intel_uxa.c @@ -209,7 +209,7 @@ intel_uxa_pixmap_compute_size(PixmapPtr pixmap, tile_height = 8; else tile_height = 32; - aligned_h = ALIGN(h, tile_height); + aligned_h = ALIGN(h, 2*tile_height); *stride = intel_get_fence_pitch(intel, ALIGN(pitch, 512),