diff mbox

[RFC] drm/radeon: add helpers for masking and setting bits in regs

Message ID 1365342564-8785-1-git-send-email-zajec5@gmail.com (mailing list archive)
State New, archived
Headers show

Commit Message

Rafał Miłecki April 7, 2013, 1:49 p.m. UTC 
---
 drivers/gpu/drm/radeon/r600_hdmi.c |   16 ++++++----------
 drivers/gpu/drm/radeon/radeon.h    |    2 ++
 2 files changed, 8 insertions(+), 10 deletions(-)

Comments

Michel Dänzer April 8, 2013, 7:49 a.m. UTC | #1 
On Son, 2013-04-07 at 15:49 +0200, Rafa? Mi?ecki wrote: 
> ---
>  drivers/gpu/drm/radeon/r600_hdmi.c |   16 ++++++----------
>  drivers/gpu/drm/radeon/radeon.h    |    2 ++
>  2 files changed, 8 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c
> index 21ecc0e..91582a5 100644
> --- a/drivers/gpu/drm/radeon/r600_hdmi.c
> +++ b/drivers/gpu/drm/radeon/r600_hdmi.c
> @@ -437,17 +437,15 @@ void r600_hdmi_enable(struct drm_encoder *encoder)
>                 hdmi = HDMI0_ERROR_ACK | HDMI0_ENABLE;
>                 switch (radeon_encoder->encoder_id) {
>                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
> -                       WREG32_P(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN,
> -                                ~AVIVO_TMDSA_CNTL_HDMI_EN);
> +                       WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN);
>                         hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA);
>                         break;
>                 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
> -                       WREG32_P(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN,
> -                                ~AVIVO_LVTMA_CNTL_HDMI_EN);
> +                       WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN);
>                         hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA);
>                         break;
>                 case ENCODER_OBJECT_ID_INTERNAL_DDI:
> -                       WREG32_P(DDIA_CNTL, DDIA_HDMI_EN, ~DDIA_HDMI_EN);
> +                       WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN);
>                         hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA);
>                         break;
>                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
> @@ -504,15 +502,13 @@ void r600_hdmi_disable(struct drm_encoder *encoder)
>         if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) {
>                 switch (radeon_encoder->encoder_id) {
>                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
> -                       WREG32_P(AVIVO_TMDSA_CNTL, 0,
> -                                ~AVIVO_TMDSA_CNTL_HDMI_EN);
> +                       WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN);
>                         break;
>                 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
> -                       WREG32_P(AVIVO_LVTMA_CNTL, 0,
> -                                ~AVIVO_LVTMA_CNTL_HDMI_EN);
> +                       WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN);
>                         break;
>                 case ENCODER_OBJECT_ID_INTERNAL_DDI:
> -                       WREG32_P(DDIA_CNTL, 0, ~DDIA_HDMI_EN);
> +                       WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN);
>                         break;
>                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
>                         break;
> diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
> index 8263af3..1f4559b 100644
> --- a/drivers/gpu/drm/radeon/radeon.h
> +++ b/drivers/gpu/drm/radeon/radeon.h
> @@ -1697,6 +1697,8 @@ void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
>                 tmp_ |= ((val) & ~(mask));                      \
>                 WREG32(reg, tmp_);                              \
>         } while (0)
> +#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
> +#define WREG32_OR(reg, or) WREG32_P(reg, or, ~or)
>  #define WREG32_PLL_P(reg, val, mask)                           \
>         do {                                                    \
>                 uint32_t tmp_ = RREG32_PLL(reg);                \

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
diff mbox

Patch

diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c
index 21ecc0e..91582a5 100644
--- a/drivers/gpu/drm/radeon/r600_hdmi.c
+++ b/drivers/gpu/drm/radeon/r600_hdmi.c
@@ -437,17 +437,15 @@  void r600_hdmi_enable(struct drm_encoder *encoder)
 		hdmi = HDMI0_ERROR_ACK | HDMI0_ENABLE;
 		switch (radeon_encoder->encoder_id) {
 		case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
-			WREG32_P(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN,
-				 ~AVIVO_TMDSA_CNTL_HDMI_EN);
+			WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN);
 			hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA);
 			break;
 		case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
-			WREG32_P(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN,
-				 ~AVIVO_LVTMA_CNTL_HDMI_EN);
+			WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN);
 			hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA);
 			break;
 		case ENCODER_OBJECT_ID_INTERNAL_DDI:
-			WREG32_P(DDIA_CNTL, DDIA_HDMI_EN, ~DDIA_HDMI_EN);
+			WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN);
 			hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA);
 			break;
 		case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
@@ -504,15 +502,13 @@  void r600_hdmi_disable(struct drm_encoder *encoder)
 	if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) {
 		switch (radeon_encoder->encoder_id) {
 		case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
-			WREG32_P(AVIVO_TMDSA_CNTL, 0,
-				 ~AVIVO_TMDSA_CNTL_HDMI_EN);
+			WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN);
 			break;
 		case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
-			WREG32_P(AVIVO_LVTMA_CNTL, 0,
-				 ~AVIVO_LVTMA_CNTL_HDMI_EN);
+			WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN);
 			break;
 		case ENCODER_OBJECT_ID_INTERNAL_DDI:
-			WREG32_P(DDIA_CNTL, 0, ~DDIA_HDMI_EN);
+			WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN);
 			break;
 		case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 			break;
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 8263af3..1f4559b 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1697,6 +1697,8 @@  void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
 		tmp_ |= ((val) & ~(mask));			\
 		WREG32(reg, tmp_);				\
 	} while (0)
+#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
+#define WREG32_OR(reg, or) WREG32_P(reg, or, ~or)
 #define WREG32_PLL_P(reg, val, mask)				\
 	do {							\
 		uint32_t tmp_ = RREG32_PLL(reg);		\