From patchwork Sun Apr 7 13:49:24 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= X-Patchwork-Id: 2403041 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id 5C112DF2A1 for ; Sun, 7 Apr 2013 13:49:43 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3E3F5E5F2B for ; Sun, 7 Apr 2013 06:49:43 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-ee0-f46.google.com (mail-ee0-f46.google.com [74.125.83.46]) by gabe.freedesktop.org (Postfix) with ESMTP id EFCB2E5CEB for ; Sun, 7 Apr 2013 06:49:32 -0700 (PDT) Received: by mail-ee0-f46.google.com with SMTP id d49so970129eek.5 for ; Sun, 07 Apr 2013 06:49:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer; bh=LZYMFOJTyAnmViN8kXkddq1XfLS4j4aol1UDxIhM3Ws=; b=ntXsuTcQWhB5/bU7WW1dk8V0SlE3MrQzfSv2v9MI7ZA+7MFcil2Umg0J7ZIZZn5wkc jG5Ptd5J6YryiBXCyVSRMg+XATyRoCsBkdkvbeiR414GA7GDM7f8kq3Fcbzkfr1aODxL R9YJ0YlnOBcvkl3Yd86I9aezXVry8ZOvi6aGL5FPRdrrfrKNkts9vlf5XA9jejWCBfJe B3KY0qvvro7dFI6gV5hV9dQ3hXMoGkIqPnGCxj9f/bV9lG6v8FhbtYhLnQm68g6YLBRs ERkU0GhVyh0/RD+wUzUpDrJtKVDHFQc49//Mv+IMOo4leaCCkF8eXFF3yBEwyQz4VRjx C5dQ== X-Received: by 10.15.107.205 with SMTP id cb53mr39001829eeb.14.1365342571817; Sun, 07 Apr 2013 06:49:31 -0700 (PDT) Received: from linux-samsung700g7a.lan (ip-194-187-74-233.konfederacka.maverick.com.pl. [194.187.74.233]) by mx.google.com with ESMTPS id cb50sm4660072eeb.14.2013.04.07.06.49.29 (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 07 Apr 2013 06:49:30 -0700 (PDT) From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= To: dri-devel@lists.freedesktop.org, Dave Airlie , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= Subject: [RFC][PATCH] drm/radeon: add helpers for masking and setting bits in regs Date: Sun, 7 Apr 2013 15:49:24 +0200 Message-Id: <1365342564-8785-1-git-send-email-zajec5@gmail.com> X-Mailer: git-send-email 1.7.10.4 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org Errors-To: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org --- drivers/gpu/drm/radeon/r600_hdmi.c | 16 ++++++---------- drivers/gpu/drm/radeon/radeon.h | 2 ++ 2 files changed, 8 insertions(+), 10 deletions(-) Reviewed-by: Michel Dänzer diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c index 21ecc0e..91582a5 100644 --- a/drivers/gpu/drm/radeon/r600_hdmi.c +++ b/drivers/gpu/drm/radeon/r600_hdmi.c @@ -437,17 +437,15 @@ void r600_hdmi_enable(struct drm_encoder *encoder) hdmi = HDMI0_ERROR_ACK | HDMI0_ENABLE; switch (radeon_encoder->encoder_id) { case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: - WREG32_P(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN, - ~AVIVO_TMDSA_CNTL_HDMI_EN); + WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN); hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA); break; case ENCODER_OBJECT_ID_INTERNAL_LVTM1: - WREG32_P(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN, - ~AVIVO_LVTMA_CNTL_HDMI_EN); + WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN); hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA); break; case ENCODER_OBJECT_ID_INTERNAL_DDI: - WREG32_P(DDIA_CNTL, DDIA_HDMI_EN, ~DDIA_HDMI_EN); + WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN); hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA); break; case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: @@ -504,15 +502,13 @@ void r600_hdmi_disable(struct drm_encoder *encoder) if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) { switch (radeon_encoder->encoder_id) { case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: - WREG32_P(AVIVO_TMDSA_CNTL, 0, - ~AVIVO_TMDSA_CNTL_HDMI_EN); + WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN); break; case ENCODER_OBJECT_ID_INTERNAL_LVTM1: - WREG32_P(AVIVO_LVTMA_CNTL, 0, - ~AVIVO_LVTMA_CNTL_HDMI_EN); + WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN); break; case ENCODER_OBJECT_ID_INTERNAL_DDI: - WREG32_P(DDIA_CNTL, 0, ~DDIA_HDMI_EN); + WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN); break; case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: break; diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 8263af3..1f4559b 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -1697,6 +1697,8 @@ void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); tmp_ |= ((val) & ~(mask)); \ WREG32(reg, tmp_); \ } while (0) +#define WREG32_AND(reg, and) WREG32_P(reg, 0, and) +#define WREG32_OR(reg, or) WREG32_P(reg, or, ~or) #define WREG32_PLL_P(reg, val, mask) \ do { \ uint32_t tmp_ = RREG32_PLL(reg); \