From patchwork Tue May 14 16:18:32 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Deucher X-Patchwork-Id: 2567361 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id B5F70DF24C for ; Tue, 14 May 2013 16:19:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6D2B2E6230 for ; Tue, 14 May 2013 09:19:49 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-qe0-f41.google.com (mail-qe0-f41.google.com [209.85.128.41]) by gabe.freedesktop.org (Postfix) with ESMTP id 5B8C7E5F2D for ; Tue, 14 May 2013 09:18:47 -0700 (PDT) Received: by mail-qe0-f41.google.com with SMTP id b10so570410qen.14 for ; Tue, 14 May 2013 09:18:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=6hqTWsGyfcOh+hpyEqdkp994jeUwrHrtEA0JZyLTwPk=; b=OQHkMZ6WoyU3jGHS2dZQH6uXh46Bna4XF1giDBjmAv50PYMhbifCkhVCzEZxxItwss ggDf3wJIn2keQyfV/mZf8uMSCngw6kKyqZfJtJwVmtXetB9NiNF0uZ+C+pLHol6AjisP nlVYa6JVZ0zKSRALBKV18fyENbLgvJmzobX+a9r7Ak2bM2iO8u6U+24Lhk1l09NnK9SM cBndxD3cxd21g16y0AVN1tIxOaOzLBaEmp6AvgCwl9nTqRNdT0S647jKpHl5r3pBvMom zFMLZA+85TjetjT89qtgGt+ULumI6NHjqqoeo3zWwcNBrddExnN3cr0m0e+imES6DUXh 4JlQ== X-Received: by 10.49.26.198 with SMTP id n6mr15492867qeg.16.1368548326941; Tue, 14 May 2013 09:18:46 -0700 (PDT) Received: from localhost.localdomain (static-74-96-105-49.washdc.fios.verizon.net. [74.96.105.49]) by mx.google.com with ESMTPSA id j9sm15370131qas.3.2013.05.14.09.18.46 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 14 May 2013 09:18:46 -0700 (PDT) From: alexdeucher@gmail.com To: dri-devel@lists.freedesktop.org Subject: [PATCH 2/9] drm/radeon: fill in GPU init for Hainan (v2) Date: Tue, 14 May 2013 12:18:32 -0400 Message-Id: <1368548319-23806-2-git-send-email-alexdeucher@gmail.com> X-Mailer: git-send-email 1.7.7.5 In-Reply-To: <1368548319-23806-1-git-send-email-alexdeucher@gmail.com> References: <1368478504-13798-1-git-send-email-alexdeucher@gmail.com> <1368548319-23806-1-git-send-email-alexdeucher@gmail.com> Cc: Alex Deucher X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org Errors-To: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org From: Alex Deucher v2: fix gb_addr_config value Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/si.c | 20 +++++++++++++++++++- drivers/gpu/drm/radeon/sid.h | 1 + 2 files changed, 20 insertions(+), 1 deletions(-) diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index f0b6c2f..234173e 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c @@ -2003,7 +2003,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); } } else if ((rdev->family == CHIP_VERDE) || - (rdev->family == CHIP_OLAND)) { + (rdev->family == CHIP_OLAND) || + (rdev->family == CHIP_HAINAN)) { for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { switch (reg_offset) { case 0: /* non-AA compressed depth or any compressed stencil */ @@ -2466,6 +2467,23 @@ static void si_gpu_init(struct radeon_device *rdev) rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; break; + case CHIP_HAINAN: + rdev->config.si.max_shader_engines = 1; + rdev->config.si.max_tile_pipes = 4; + rdev->config.si.max_cu_per_sh = 5; + rdev->config.si.max_sh_per_se = 1; + rdev->config.si.max_backends_per_se = 1; + rdev->config.si.max_texture_channel_caches = 2; + rdev->config.si.max_gprs = 256; + rdev->config.si.max_gs_threads = 16; + rdev->config.si.max_hw_contexts = 8; + + rdev->config.si.sc_prim_fifo_size_frontend = 0x20; + rdev->config.si.sc_prim_fifo_size_backend = 0x40; + rdev->config.si.sc_hiz_tile_fifo_size = 0x30; + rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; + gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN; + break; } /* Initialize HDP */ diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h index 222877b..8f2d7d4 100644 --- a/drivers/gpu/drm/radeon/sid.h +++ b/drivers/gpu/drm/radeon/sid.h @@ -28,6 +28,7 @@ #define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003 #define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002 +#define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02010001 /* discrete uvd clocks */ #define CG_UPLL_FUNC_CNTL 0x634