From patchwork Thu May 30 00:40:01 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Swanson X-Patchwork-Id: 2633231 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 9E71A3FC23 for ; Thu, 30 May 2013 01:00:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 365C6E657B for ; Wed, 29 May 2013 18:00:32 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org X-Greylist: delayed 1214 seconds by postgrey-1.32 at gabe; Wed, 29 May 2013 18:00:17 PDT Received: from mail.ukfsn.org (mail.ukfsn.org [77.75.108.10]) by gabe.freedesktop.org (Postfix) with ESMTP id 4AC4BE61A2 for ; Wed, 29 May 2013 18:00:17 -0700 (PDT) Received: from slartibartfast.infiniteimprobability.net (slartibartfast.infiniteimprobability.net [87.127.90.134]) by mail.ukfsn.org (Postfix) with ESMTP id 4E696C708A for ; Thu, 30 May 2013 01:40:02 +0100 (BST) Received: from [87.127.90.131] (trillian.infiniteimprobability.net [87.127.90.131]) by slartibartfast.infiniteimprobability.net (Postfix) with ESMTP id BB2601EE for ; Thu, 30 May 2013 01:40:01 +0100 (BST) Message-ID: <1369874401.7449.1.camel@trillian.infiniteimprobability.net> Subject: [PATCH] drm/radeon: restrict engine clock to fastest power state From: Alan Swanson To: dri-devel@lists.freedesktop.org Date: Thu, 30 May 2013 01:40:01 +0100 X-Mailer: Evolution 3.6.4 Mime-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org Errors-To: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org Radeon power management restricts the maximum engine clock to the initial default clock. However, on APUs the default clock usually is not the fastest allowed by their defined power states. Change restriction to the fastest engine clock found in power states. Signed-off-by: Alan Swanson --- drivers/gpu/drm/radeon/radeon.h | 1 + drivers/gpu/drm/radeon/radeon_pm.c | 25 ++++++++++++++++++++++--- 2 files changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 1442ce7..83d1e76 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -1111,6 +1111,7 @@ struct radeon_pm { u32 default_mclk; u16 default_vddc; u16 default_vddci; + u32 max_sclk; struct radeon_i2c_chan *i2c_bus; /* selected pm method */ enum radeon_pm_method pm_method; diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c index 788c64c..3512af9 100644 --- a/drivers/gpu/drm/radeon/radeon_pm.c +++ b/drivers/gpu/drm/radeon/radeon_pm.c @@ -164,8 +164,8 @@ static void radeon_set_power_state(struct radeon_device *rdev) if (radeon_gui_idle(rdev)) { sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. clock_info[rdev->pm.requested_clock_mode_index].sclk; - if (sclk > rdev->pm.default_sclk) - sclk = rdev->pm.default_sclk; + if (sclk > rdev->pm.max_sclk) + sclk = rdev->pm.max_sclk; /* starting with BTC, there is one state that is used for both * MH and SH. Difference is that we always use the high clock index for @@ -307,7 +307,7 @@ static void radeon_pm_print_states(struct radeon_device *rdev) DRM_DEBUG_DRIVER("State %d: %s\n", i, radeon_pm_state_type_name[power_state->type]); if (i == rdev->pm.default_power_state_index) - DRM_DEBUG_DRIVER("\tDefault"); + DRM_DEBUG_DRIVER("\tDEFAULT\n"); if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP)) DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes); if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) @@ -329,6 +329,22 @@ static void radeon_pm_print_states(struct radeon_device *rdev) } } +static void radeon_pm_get_max_clocks(struct radeon_device *rdev) +{ + int i, j; + struct radeon_power_state *power_state; + struct radeon_pm_clock_info *clock_info; + + for (i = 0; i < rdev->pm.num_power_states; i++) { + power_state = &rdev->pm.power_state[i]; + for (j = 0; j < power_state->num_clock_modes; j++) { + clock_info = &(power_state->clock_info[j]); + if (clock_info->sclk > rdev->pm.max_sclk) + rdev->pm.max_sclk = clock_info->sclk; + } + } +} + static ssize_t radeon_get_pm_profile(struct device *dev, struct device_attribute *attr, char *buf) @@ -588,6 +604,7 @@ int radeon_pm_init(struct radeon_device *rdev) rdev->pm.default_mclk = rdev->clock.default_mclk; rdev->pm.current_sclk = rdev->clock.default_sclk; rdev->pm.current_mclk = rdev->clock.default_mclk; + rdev->pm.max_sclk = rdev->clock.default_sclk; rdev->pm.int_thermal_type = THERMAL_TYPE_NONE; if (rdev->bios) { @@ -597,6 +614,7 @@ int radeon_pm_init(struct radeon_device *rdev) radeon_combios_get_power_modes(rdev); radeon_pm_print_states(rdev); radeon_pm_init_profile(rdev); + radeon_pm_get_max_clocks(rdev); /* set up the default clocks if the MC ucode is loaded */ if ((rdev->family >= CHIP_BARTS) && (rdev->family <= CHIP_CAYMAN) && @@ -848,6 +866,7 @@ static int radeon_debugfs_pm_info(struct seq_file *m, void *data) seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk); else seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev)); + seq_printf(m, "maximum engine clock: %u0 kHz\n", rdev->pm.max_sclk); seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk); if (rdev->asic->pm.get_memory_clock) seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));