From patchwork Mon Jun 10 11:00:59 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Sharma X-Patchwork-Id: 2696961 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id 7073DDF264 for ; Mon, 10 Jun 2013 11:13:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6318AE629D for ; Mon, 10 Jun 2013 04:13:46 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mailout3.samsung.com (mailout3.samsung.com [203.254.224.33]) by gabe.freedesktop.org (Postfix) with ESMTP id 199F1E5EDB for ; Mon, 10 Jun 2013 03:40:15 -0700 (PDT) Received: from epcpsbgr5.samsung.com (u145.gpu120.samsung.co.kr [203.254.230.145]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MO6008NAAZ143L0@mailout3.samsung.com> for dri-devel@lists.freedesktop.org; Mon, 10 Jun 2013 19:40:14 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.126]) by epcpsbgr5.samsung.com (EPCPMTA) with SMTP id AF.A9.11618.E0DA5B15; Mon, 10 Jun 2013 19:40:14 +0900 (KST) X-AuditID: cbfee691-b7fef6d000002d62-d0-51b5ad0e418c Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id CE.79.28381.E0DA5B15; Mon, 10 Jun 2013 19:40:14 +0900 (KST) Received: from chromeserver-PowerEdge-T410.sisodomain.com ([107.108.73.106]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MO6001FHATOFA30@mmp2.samsung.com>; Mon, 10 Jun 2013 19:40:14 +0900 (KST) From: Rahul Sharma To: linux-samsung-soc@vger.kernel.org, devicetree-discuss@lists.ozlabs.org Subject: [PATCH 2/5] clk/exynos5250: add mout_hdmi mux clock for hdmi Date: Mon, 10 Jun 2013 16:30:59 +0530 Message-id: <1370862062-16680-3-git-send-email-rahul.sharma@samsung.com> X-Mailer: git-send-email 1.7.10.4 In-reply-to: <1370862062-16680-1-git-send-email-rahul.sharma@samsung.com> References: <1370862062-16680-1-git-send-email-rahul.sharma@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmplkeLIzCtJLcpLzFFi42JZI2JSp8u3dmugwZ65EhYfT91mtTgw+yGr xZWv79ksJt2fwGLxfdcXdoveBVfZLGac38dksfBFvMWURYdZLWZMfsnmwOWxc9Zddo/73ceZ PM7PWMjo0bdlFaPH501yAaxRXDYpqTmZZalF+nYJXBlbNj5lKVglWLHz0FzWBsY1fF2MnBwS AiYS8/dtZYawxSQu3FvP1sXIxSEksJRR4srZI2wwRft6vzBBJKYzSrz5OokFwpnNJPH85jEm kCo2AV2J2QefMYLYIgJeEt1rtrODFDELXGGUuHb4FliRsICrxLop04C6OThYBFQldpysAgnz CnhIXL/xnh1im6JE97MJYJs5BTwlTsw6BDZTCKjmz969zCAzJQS2sUt87noDlmAREJD4NvkQ 2EwJAVmJTQeg3pGUOLjiBssERuEFjAyrGEVTC5ILipPSi0z1ihNzi0vz0vWS83M3MQKj4PS/ ZxN3MN4/YH2IMRlo3ERmKdHkfGAU5ZXEGxqbGVmYmpgaG5lbmpEmrCTOq95iHSgkkJ5Ykpqd mlqQWhRfVJqTWnyIkYmDU6qB8VTd5BW1N5YcYS9SNFvTcvY545Oo/L9bXvj8eyVwM6lZQ8v6 zcYT0sV7Vs+xE/0Qv/Zv4k1n8TMaEx6+q8j0L/46Me2kh0jvpQOdXSlmG9jui/spH9W9OD3V JXDWc1atU/JSbGmt7o/9MkqN+wODf0YccuntctdYt27qEttTT56skrTdNTdmmRJLcUaioRZz UXEiADu5HseYAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrEIsWRmVeSWpSXmKPExsVy+t9jQV2+tVsDDW795rP4eOo2q8WB2Q9Z La58fc9mMen+BBaL77u+sFv0LrjKZjHj/D4mi4Uv4i2mLDrMajFj8ks2By6PnbPusnvc7z7O 5HF+xkJGj74tqxg9Pm+SC2CNamC0yUhNTEktUkjNS85PycxLt1XyDo53jjc1MzDUNbS0MFdS yEvMTbVVcvEJ0HXLzAG6SkmhLDGnFCgUkFhcrKRvh2lCaIibrgVMY4Sub0gQXI+RARpIWMOY sWXjU5aCVYIVOw/NZW1gXMPXxcjJISFgIrGv9wsThC0mceHeerYuRi4OIYHpjBJvvk5igXBm M0k8v3kMrIpNQFdi9sFnjCC2iICXRPea7ewgRcwCVxglrh2+BVYkLOAqsW7KNKBuDg4WAVWJ HSerQMK8Ah4S12+8Z4fYpijR/WwCG4jNKeApcWLWIbCZQkA1f/buZZ7AyLuAkWEVo2hqQXJB cVJ6rqFecWJucWleul5yfu4mRnCMPZPawbiyweIQowAHoxIP74NfWwKFWBPLiitzDzFKcDAr ifAWz9oaKMSbklhZlVqUH19UmpNafIgxGeioicxSosn5wPjPK4k3NDYxNzU2tTSxMDGzJE1Y SZz3QKt1oJBAemJJanZqakFqEcwWJg5OqQZGuU3Fyvu9TBmZZS9euf0yW//QlytZoZcYjhe9 sF80lc9jz4zurfx5OeLvk9eelS499CDxwrJfF+1cXybJhWWumn/EZePswqkMvbOFOj/LdV/7 cTFj4dlT7LXTtK/ZhnTlsT+4c0OjUfgwd+4CDY8Ncn63J3zecJUz4mHwh1oOmZP6P0TfquZu UGIpzkg01GIuKk4EALPNKEv1AgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-Mailman-Approved-At: Mon, 10 Jun 2013 04:10:07 -0700 Cc: kgene.kim@samsung.com, sw0312.kim@samsung.com, joshi@samsung.com, dri-devel@lists.freedesktop.org, arun.kk@samsung.com, Rahul Sharma X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org Errors-To: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org hdmi driver needs to change the parent of hdmi clock frequently between pixel clock and hdmiphy clock. hdmiphy is not stable after power on and for a short interval while changing the phy configuration. For this duration pixel clock is used to clock hdmi. This patch is exposing the mux for changing parent. Signed-off-by: Rahul Sharma --- Documentation/devicetree/bindings/clock/exynos5250-clock.txt | 8 ++++++++ drivers/clk/samsung/clk-exynos5250.c | 5 ++++- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt index 1a05761..b337147 100644 --- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt @@ -156,6 +156,14 @@ clock which they consume. mixer 343 hdmi 344 + + [Clock Muxes] + + Clock ID + ---------------------------- + mout_hdmi 1024 + + Example 1: An example of a clock controller node is listed below. clock: clock-controller@0x10010000 { diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 5c97e75..587d913 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -100,6 +100,9 @@ enum exynos5250_clks { tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct, wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, + /* mux clocks */ + mout_hdmi = 1024, + nr_clks, }; @@ -231,7 +234,7 @@ struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { MUX(none, "mout_fimd1", mout_group1_p, SRC_DISP1_0, 0, 4), MUX(none, "mout_mipi1", mout_group1_p, SRC_DISP1_0, 12, 4), MUX(none, "mout_dp", mout_group1_p, SRC_DISP1_0, 16, 4), - MUX(none, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1), + MUX(mout_hdmi, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1), MUX(none, "mout_audio0", mout_audio0_p, SRC_MAU, 0, 4), MUX(none, "mout_mmc0", mout_group1_p, SRC_FSYS, 0, 4), MUX(none, "mout_mmc1", mout_group1_p, SRC_FSYS, 4, 4),