From patchwork Tue Jun 11 06:54:02 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Sharma X-Patchwork-Id: 2703091 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 467883FD4E for ; Tue, 11 Jun 2013 12:45:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 19E27E63B6 for ; Tue, 11 Jun 2013 05:45:36 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mailout4.samsung.com (mailout4.samsung.com [203.254.224.34]) by gabe.freedesktop.org (Postfix) with ESMTP id AFCE4E5E0A for ; Mon, 10 Jun 2013 23:30:18 -0700 (PDT) Received: from epcpsbgr5.samsung.com (u145.gpu120.samsung.co.kr [203.254.230.145]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MO700FSWU1X8420@mailout4.samsung.com> for dri-devel@lists.freedesktop.org; Tue, 11 Jun 2013 15:30:16 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.126]) by epcpsbgr5.samsung.com (EPCPMTA) with SMTP id 2F.F4.11618.8F3C6B15; Tue, 11 Jun 2013 15:30:16 +0900 (KST) X-AuditID: cbfee691-b7fef6d000002d62-9e-51b6c3f83908 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 96.84.21068.8F3C6B15; Tue, 11 Jun 2013 15:30:16 +0900 (KST) Received: from chromeserver-PowerEdge-T410.sisodomain.com ([107.108.73.106]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MO7005T7U24EVB1@mmp2.samsung.com>; Tue, 11 Jun 2013 15:30:16 +0900 (KST) From: Rahul Sharma To: linux-samsung-soc@vger.kernel.org, devicetree-discuss@lists.ozlabs.org, dri-devel@lists.freedesktop.org Subject: [PATCH 1/4] drm/exynos: Prepare/Unprepare HDMI subsystem clocks Date: Tue, 11 Jun 2013 12:24:02 +0530 Message-id: <1370933645-18344-2-git-send-email-rahul.sharma@samsung.com> X-Mailer: git-send-email 1.7.10.4 In-reply-to: <1370933645-18344-1-git-send-email-rahul.sharma@samsung.com> References: <1370933645-18344-1-git-send-email-rahul.sharma@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupikeLIzCtJLcpLzFFi42JZI2JSp/vj8LZAgz13dC0OzH7IanHl63s2 i0n3J7BYfN/1hd2id8FVNosZ5/cxWSx8EW8xZdFhVou7G84yWsyY/JLNgctjdsNFFo+ds+6y e9zvPs7kcX7GQkaPvi2rGD0+b5ILYIvisklJzcksSy3St0vgythxZCVzwVO5inUTHzI3MD6T 6mLk5JAQMJG4NWUxE4QtJnHh3nq2LkYuDiGBpYwSPy4fYIMpWjPlNSuILSQwnVHi1nxHiKLZ TBLru8+xgyTYBHQlZh98xghiiwjkSjT8bWcBKWIW2MwocX/7NxaQhLCAh8SH54vBGlgEVCWO /fwOFucFivfcfwh1hqJE97MJYJs5BTwlOt+2MEFs9pC4uWsf2HkSAtvYJa4sPMQMMUhA4tvk Q0CDOIASshKbDjBDzJGUOLjiBssERuEFjAyrGEVTC5ILipPSi0z1ihNzi0vz0vWS83M3MQLj 4fS/ZxN3MN4/YH2IMRlo3ERmKdHkfGA85ZXEGxqbGVmYmpgaG5lbmpEmrCTOq95iHSgkkJ5Y kpqdmlqQWhRfVJqTWnyIkYmDU6qBkY+hTfLr7UvXfLMZRezevDX03LFwZ1yS3M21dYVccokB Ufmz9fa082+4mvmr8r7be/GwFbsuHE1+PJ21YLumudD0gw8fm/+cq24vplHcxW6a/qet5eHb c48np9pdVdim82rP/VL+o9NmFS1jOn5oo9vmsElr2GqKZ+6SlLjlbz7dfafuV7fQPiWW4oxE Qy3mouJEALzyz1GdAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrOIsWRmVeSWpSXmKPExsVy+t9jQd0fh7cFGsztV7Q4MPshq8WVr+/Z LCbdn8Bi8X3XF3aL3gVX2SxmnN/HZLHwRbzFlEWHWS3ubjjLaDFj8ks2By6P2Q0XWTx2zrrL 7nG/+ziTx/kZCxk9+rasYvT4vEkugC2qgdEmIzUxJbVIITUvOT8lMy/dVsk7ON453tTMwFDX 0NLCXEkhLzE31VbJxSdA1y0zB+g0JYWyxJxSoFBAYnGxkr4dpgmhIW66FjCNEbq+IUFwPUYG aCBhDWPGjiMrmQueylWsm/iQuYHxmVQXIyeHhICJxJopr1khbDGJC/fWs4HYQgLTGSVuzXfs YuQCsmczSazvPscOkmAT0JWYffAZI4gtIpAr0fC3nQWkiFlgM6PE/e3fWEASwgIeEh+eLwZr YBFQlTj28ztYnBco3nP/IRPENkWJ7mcTwLZxCnhKdL5tYYLY7CFxc9c+tgmMvAsYGVYxiqYW JBcUJ6XnGukVJ+YWl+al6yXn525iBEfbM+kdjKsaLA4xCnAwKvHwJjBuCxRiTSwrrsw9xCjB wawkwmu6HSjEm5JYWZValB9fVJqTWnyIMRnoqonMUqLJ+cBEkFcSb2hsYm5qbGppYmFiZkma sJI478FW60AhgfTEktTs1NSC1CKYLUwcnFINjMr1npf1Fp7T4jCJT+7Jzv/9uIotRODIxUUM 039MVo/czV/cGi9nbc/1aFpGolee9gaDdRozxBa7nhJawOBinNgQv0fhIYv4+orn/M9C3k40 WHZb7sjt/V6uJskLjOPMHxyXktospmJsqpAzSZTJkr9j+YKFknxvp8zf+HqeuNel7J1vHsk2 KrEUZyQaajEXFScCAHD6Hbr6AgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-Mailman-Approved-At: Tue, 11 Jun 2013 05:45:11 -0700 Cc: kgene.kim@samsung.com, sw0312.kim@samsung.com, joshi@samsung.com, Rahul Sharma X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org Errors-To: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org From: Sean Paul Change the clk_enable/clk_disable calls in mixer and hdmi drivers into clk_prepare_enable/clk_disable_unprepare, respectively. Signed-off-by: Sean Paul Signed-off-by: Rahul Sharma --- drivers/gpu/drm/exynos/exynos_hdmi.c | 24 ++++++++++++------------ drivers/gpu/drm/exynos/exynos_mixer.c | 12 ++++++------ 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c index 04255fe..5a98194 100644 --- a/drivers/gpu/drm/exynos/exynos_hdmi.c +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c @@ -1117,9 +1117,9 @@ static void hdmi_v13_mode_apply(struct hdmi_context *hdata) hdmi_regs_dump(hdata, "timing apply"); } - clk_disable(hdata->res.sclk_hdmi); + clk_disable_unprepare(hdata->res.sclk_hdmi); clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_hdmiphy); - clk_enable(hdata->res.sclk_hdmi); + clk_prepare_enable(hdata->res.sclk_hdmi); /* enable HDMI and timing generator */ hdmi_reg_writemask(hdata, HDMI_CON_0, ~0, HDMI_EN); @@ -1284,9 +1284,9 @@ static void hdmi_v14_mode_apply(struct hdmi_context *hdata) hdmi_regs_dump(hdata, "timing apply"); } - clk_disable(hdata->res.sclk_hdmi); + clk_disable_unprepare(hdata->res.sclk_hdmi); clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_hdmiphy); - clk_enable(hdata->res.sclk_hdmi); + clk_prepare_enable(hdata->res.sclk_hdmi); /* enable HDMI and timing generator */ hdmi_reg_writemask(hdata, HDMI_CON_0, ~0, HDMI_EN); @@ -1310,9 +1310,9 @@ static void hdmiphy_conf_reset(struct hdmi_context *hdata) u8 buffer[2]; u32 reg; - clk_disable(hdata->res.sclk_hdmi); + clk_disable_unprepare(hdata->res.sclk_hdmi); clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_pixel); - clk_enable(hdata->res.sclk_hdmi); + clk_prepare_enable(hdata->res.sclk_hdmi); /* operation mode */ buffer[0] = 0x1f; @@ -1701,9 +1701,9 @@ static void hdmi_poweron(struct hdmi_context *hdata) if (regulator_bulk_enable(res->regul_count, res->regul_bulk)) DRM_DEBUG_KMS("failed to enable regulator bulk\n"); - clk_enable(res->hdmiphy); - clk_enable(res->hdmi); - clk_enable(res->sclk_hdmi); + clk_prepare_enable(res->hdmiphy); + clk_prepare_enable(res->hdmi); + clk_prepare_enable(res->sclk_hdmi); hdmiphy_poweron(hdata); } @@ -1726,9 +1726,9 @@ static void hdmi_poweroff(struct hdmi_context *hdata) hdmiphy_conf_reset(hdata); hdmiphy_poweroff(hdata); - clk_disable(res->sclk_hdmi); - clk_disable(res->hdmi); - clk_disable(res->hdmiphy); + clk_disable_unprepare(res->sclk_hdmi); + clk_disable_unprepare(res->hdmi); + clk_disable_unprepare(res->hdmiphy); regulator_bulk_disable(res->regul_count, res->regul_bulk); mutex_lock(&hdata->hdmi_mutex); diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c index b0882b3..978894e 100644 --- a/drivers/gpu/drm/exynos/exynos_mixer.c +++ b/drivers/gpu/drm/exynos/exynos_mixer.c @@ -900,10 +900,10 @@ static void mixer_poweron(struct mixer_context *ctx) ctx->powered = true; mutex_unlock(&ctx->mixer_mutex); - clk_enable(res->mixer); + clk_prepare_enable(res->mixer); if (ctx->vp_enabled) { - clk_enable(res->vp); - clk_enable(res->sclk_mixer); + clk_prepare_enable(res->vp); + clk_prepare_enable(res->sclk_mixer); } mixer_reg_write(res, MXR_INT_EN, ctx->int_en); @@ -927,10 +927,10 @@ static void mixer_poweroff(struct mixer_context *ctx) ctx->int_en = mixer_reg_read(res, MXR_INT_EN); - clk_disable(res->mixer); + clk_disable_unprepare(res->mixer); if (ctx->vp_enabled) { - clk_disable(res->vp); - clk_disable(res->sclk_mixer); + clk_disable_unprepare(res->vp); + clk_disable_unprepare(res->sclk_mixer); } mutex_lock(&ctx->mixer_mutex);