From patchwork Tue Jun 11 06:54:03 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Sharma X-Patchwork-Id: 2703101 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id E9441DF23A for ; Tue, 11 Jun 2013 12:47:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DEB42E63BD for ; Tue, 11 Jun 2013 05:47:09 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mailout3.samsung.com (mailout3.samsung.com [203.254.224.33]) by gabe.freedesktop.org (Postfix) with ESMTP id 48C67E5F9A for ; Mon, 10 Jun 2013 23:30:24 -0700 (PDT) Received: from epcpsbgr2.samsung.com (u142.gpu120.samsung.co.kr [203.254.230.142]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MO70042MU2BUVP0@mailout3.samsung.com> for dri-devel@lists.freedesktop.org; Tue, 11 Jun 2013 15:30:18 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.124]) by epcpsbgr2.samsung.com (EPCPMTA) with SMTP id 30.D0.08825.AF3C6B15; Tue, 11 Jun 2013 15:30:18 +0900 (KST) X-AuditID: cbfee68e-b7f276d000002279-67-51b6c3fa3684 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 43.40.28381.AF3C6B15; Tue, 11 Jun 2013 15:30:18 +0900 (KST) Received: from chromeserver-PowerEdge-T410.sisodomain.com ([107.108.73.106]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MO7005T7U24EVB1@mmp2.samsung.com>; Tue, 11 Jun 2013 15:30:18 +0900 (KST) From: Rahul Sharma To: linux-samsung-soc@vger.kernel.org, devicetree-discuss@lists.ozlabs.org, dri-devel@lists.freedesktop.org Subject: [PATCH 2/4] drm/exynos: add mout_hdmi clock in hdmi driver to change parent Date: Tue, 11 Jun 2013 12:24:03 +0530 Message-id: <1370933645-18344-3-git-send-email-rahul.sharma@samsung.com> X-Mailer: git-send-email 1.7.10.4 In-reply-to: <1370933645-18344-1-git-send-email-rahul.sharma@samsung.com> References: <1370933645-18344-1-git-send-email-rahul.sharma@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupgkeLIzCtJLcpLzFFi42JZI2JSo/vr8LZAg2t7DS0OzH7IanHl63s2 i0n3J7BYfN/1hd2id8FVNosZ5/cxWSx8EW8xZdFhVou7G84yWsyY/JLNgctjdsNFFo+ds+6y e9zvPs7kcX7GQkaPvi2rGD0+b5ILYIvisklJzcksSy3St0vgyvix6hJbwSKhinsHZzA1MJ7k 72Lk4JAQMJG43MPbxcgJZIpJXLi3nq2LkYtDSGApo8TrVYeZIRImEnd+H2aFSExnlOj89YgR wpnNJHGu6SpYFZuArsTsg88YQWwRgVyJhr/tLCBFzAKbGSXub//GArJOWCBM4vqFfJAaFgFV iQ/tM8DqeQU8JO61TGGE2KYo0f1sAhuIzSngKdH5toUJxBYCqrm5ax8bRM0+dokrp2oh5ghI fJt8iAXiG1mJTQegjpaUOLjiBssERuEFjAyrGEVTC5ILipPSi4z0ihNzi0vz0vWS83M3MQJj 4fS/Z307GG8esD7EmAw0biKzlGhyPjCW8kriDY3NjCxMTUyNjcwtzUgTVhLnVWuxDhQSSE8s Sc1OTS1ILYovKs1JLT7EyMTBKdXAuInLdMO/z06aAXnLCz4duLFNrubcvYa+6TsuFdketUp4 u2DW3OKDAbYRiyb8PPDw+dSuyOWnhFm4yid51IaHSKgc5fl3t850l/ti9d3zF3ZuWb9nzy63 nA71K0IsK+27r8rfzQ9feafrAPudI4/z7e9um5O4pf+n9aYpZ70mHdWQdevzr8zqM1ZiKc5I NNRiLipOBABUix+imwIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrOIsWRmVeSWpSXmKPExsVy+t9jQd1fh7cFGpzfomFxYPZDVosrX9+z WUy6P4HF4vuuL+wWvQuuslnMOL+PyWLhi3iLKYsOs1rc3XCW0WLG5JdsDlwesxsusnjsnHWX 3eN+93Emj/MzFjJ69G1ZxejxeZNcAFtUA6NNRmpiSmqRQmpecn5KZl66rZJ3cLxzvKmZgaGu oaWFuZJCXmJuqq2Si0+ArltmDtBpSgpliTmlQKGAxOJiJX07TBNCQ9x0LWAaI3R9Q4LgeowM 0EDCGsaMH6susRUsEqq4d3AGUwPjSf4uRk4OCQETiTu/D7NC2GISF+6tZ+ti5OIQEpjOKNH5 6xEjhDObSeJc01VmkCo2AV2J2QefMYLYIgK5Eg1/21lAipgFNjNK3N/+Dcjh4BAWCJO4fiEf pIZFQFXiQ/sMsHpeAQ+Jey1TGCG2KUp0P5vABmJzCnhKdL5tYQKxhYBqbu7axzaBkXcBI8Mq RtHUguSC4qT0XEO94sTc4tK8dL3k/NxNjOBoeya1g3Flg8UhRgEORiUe3gTGbYFCrIllxZW5 hxglOJiVRHhNtwOFeFMSK6tSi/Lji0pzUosPMSYDXTWRWUo0OR+YCPJK4g2NTcxNjU0tTSxM zCxJE1YS5z3Qah0oJJCeWJKanZpakFoEs4WJg1OqgXHNUYV/p3Nubl1sqTSF4a3K1C3JGTXL QlpVtVeyTdqk57LY5NGuCVsilF4eEq3Ntp/sWfVPc6Nt4ooWs5s1fxvZ9l8WmRn2dE3g7c2L Nua+OVTQ2VWxq+xM1WGZTdlsO3v5az5ozXl7oNnhQcXXmOXv/UOWH+mx0ForlWwldr2lWKnE a71o7holluKMREMt5qLiRAAsQ8lN+gIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-Mailman-Approved-At: Tue, 11 Jun 2013 05:45:11 -0700 Cc: kgene.kim@samsung.com, sw0312.kim@samsung.com, joshi@samsung.com, Rahul Sharma X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org Errors-To: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org HDMI driver needs to configure the mout_hdmi mux clock to change the parent between sclk_hdmiphy and sclk_pixel. Signed-off-by: Rahul Sharma --- drivers/gpu/drm/exynos/exynos_hdmi.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c index 5a98194..3b5e215 100644 --- a/drivers/gpu/drm/exynos/exynos_hdmi.c +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c @@ -83,6 +83,7 @@ struct hdmi_resources { struct clk *sclk_pixel; struct clk *sclk_hdmiphy; struct clk *hdmiphy; + struct clk *mout_hdmi; struct regulator_bulk_data *regul_bulk; int regul_count; }; @@ -1118,7 +1119,7 @@ static void hdmi_v13_mode_apply(struct hdmi_context *hdata) } clk_disable_unprepare(hdata->res.sclk_hdmi); - clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_hdmiphy); + clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_hdmiphy); clk_prepare_enable(hdata->res.sclk_hdmi); /* enable HDMI and timing generator */ @@ -1285,7 +1286,7 @@ static void hdmi_v14_mode_apply(struct hdmi_context *hdata) } clk_disable_unprepare(hdata->res.sclk_hdmi); - clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_hdmiphy); + clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_hdmiphy); clk_prepare_enable(hdata->res.sclk_hdmi); /* enable HDMI and timing generator */ @@ -1311,7 +1312,7 @@ static void hdmiphy_conf_reset(struct hdmi_context *hdata) u32 reg; clk_disable_unprepare(hdata->res.sclk_hdmi); - clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_pixel); + clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_pixel); clk_prepare_enable(hdata->res.sclk_hdmi); /* operation mode */ @@ -1832,8 +1833,13 @@ static int hdmi_resources_init(struct hdmi_context *hdata) DRM_ERROR("failed to get clock 'hdmiphy'\n"); goto fail; } + res->mout_hdmi = devm_clk_get(dev, "mout_hdmi"); + if (IS_ERR(res->mout_hdmi)) { + DRM_ERROR("failed to get clock 'mout_hdmi'\n"); + goto fail; + } - clk_set_parent(res->sclk_hdmi, res->sclk_pixel); + clk_set_parent(res->mout_hdmi, res->sclk_pixel); res->regul_bulk = devm_kzalloc(dev, ARRAY_SIZE(supply) * sizeof(res->regul_bulk[0]), GFP_KERNEL);