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[74.96.105.49]) by mx.google.com with ESMTPSA id r10sm32665096qeu.4.2013.06.26.06.25.28 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 26 Jun 2013 06:25:28 -0700 (PDT) From: alexdeucher@gmail.com To: dri-devel@lists.freedesktop.org Subject: [PATCH 108/165] drm/radeon/dpm: add pre/post_set_power_state callback (cayman) Date: Wed, 26 Jun 2013 09:23:08 -0400 Message-Id: <1372253045-17042-109-git-send-email-alexdeucher@gmail.com> X-Mailer: git-send-email 1.7.7.5 In-Reply-To: <1372253045-17042-1-git-send-email-alexdeucher@gmail.com> References: <1372253045-17042-1-git-send-email-alexdeucher@gmail.com> Cc: Alex Deucher X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org Errors-To: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Alex Deucher This properly implemented dynamic state adjustment by using a working copy of the requested and current power states. Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/ni_dpm.c | 65 ++++++++++++++++++++++++++++------ drivers/gpu/drm/radeon/ni_dpm.h | 3 +- drivers/gpu/drm/radeon/radeon_asic.c | 2 + drivers/gpu/drm/radeon/radeon_asic.h | 2 + 4 files changed, 60 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/radeon/ni_dpm.c b/drivers/gpu/drm/radeon/ni_dpm.c index ebc9837..01ecb80 100644 --- a/drivers/gpu/drm/radeon/ni_dpm.c +++ b/drivers/gpu/drm/radeon/ni_dpm.c @@ -791,7 +791,6 @@ static void ni_calculate_leakage_for_v_and_t(struct radeon_device *rdev, static void ni_apply_state_adjust_rules(struct radeon_device *rdev, struct radeon_ps *rps) { - struct ni_power_info *ni_pi = ni_get_pi(rdev); struct ni_ps *ps = ni_get_ps(rps); struct radeon_clock_and_voltage_limits *max_limits; bool disable_mclk_switching; @@ -799,11 +798,6 @@ static void ni_apply_state_adjust_rules(struct radeon_device *rdev, u16 vddc, vddci; int i; - /* point to the hw copy since this function will modify the ps */ - ni_pi->hw_ps = *ps; - rdev->pm.dpm.hw_ps.ps_priv = &ni_pi->hw_ps; - ps = &ni_pi->hw_ps; - if (rdev->pm.dpm.new_active_crtc_count > 1) disable_mclk_switching = true; else @@ -3502,6 +3496,30 @@ void ni_dpm_setup_asic(struct radeon_device *rdev) rv770_enable_acpi_pm(rdev); } +static void ni_update_current_ps(struct radeon_device *rdev, + struct radeon_ps *rps) +{ + struct ni_ps *new_ps = ni_get_ps(rps); + struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); + struct ni_power_info *ni_pi = ni_get_pi(rdev); + + eg_pi->current_rps = *rps; + ni_pi->current_ps = *new_ps; + eg_pi->current_rps.ps_priv = &ni_pi->current_ps; +} + +static void ni_update_requested_ps(struct radeon_device *rdev, + struct radeon_ps *rps) +{ + struct ni_ps *new_ps = ni_get_ps(rps); + struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); + struct ni_power_info *ni_pi = ni_get_pi(rdev); + + eg_pi->requested_rps = *rps; + ni_pi->requested_ps = *new_ps; + eg_pi->requested_rps.ps_priv = &ni_pi->requested_ps; +} + int ni_dpm_enable(struct radeon_device *rdev) { struct rv7xx_power_info *pi = rv770_get_pi(rdev); @@ -3576,6 +3594,8 @@ int ni_dpm_enable(struct radeon_device *rdev) rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); + ni_update_current_ps(rdev, boot_ps); + return 0; } @@ -3613,6 +3633,8 @@ void ni_dpm_disable(struct radeon_device *rdev) btc_reset_to_default(rdev); ni_stop_smc(rdev); ni_force_switch_to_arb_f0(rdev); + + ni_update_current_ps(rdev, boot_ps); } int ni_power_control_set_level(struct radeon_device *rdev) @@ -3628,14 +3650,25 @@ int ni_power_control_set_level(struct radeon_device *rdev) return 0; } +int ni_dpm_pre_set_power_state(struct radeon_device *rdev) +{ + struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); + struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; + struct radeon_ps *new_ps = &requested_ps; + + ni_update_requested_ps(rdev, new_ps); + + ni_apply_state_adjust_rules(rdev, &eg_pi->requested_rps); + + return 0; +} + int ni_dpm_set_power_state(struct radeon_device *rdev) { struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); - struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; + struct radeon_ps *new_ps = &eg_pi->requested_rps; int ret; - ni_apply_state_adjust_rules(rdev, new_ps); - ni_restrict_performance_levels_before_switch(rdev); ni_enable_power_containment(rdev, new_ps, false); ni_enable_smc_cac(rdev, new_ps, false); @@ -3657,6 +3690,14 @@ int ni_dpm_set_power_state(struct radeon_device *rdev) return 0; } +void ni_dpm_post_set_power_state(struct radeon_device *rdev) +{ + struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); + struct radeon_ps *new_ps = &eg_pi->requested_rps; + + ni_update_current_ps(rdev, new_ps); +} + void ni_dpm_reset_asic(struct radeon_device *rdev) { ni_restrict_performance_levels_before_switch(rdev); @@ -4078,7 +4119,8 @@ void ni_dpm_print_power_state(struct radeon_device *rdev, u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low) { - struct ni_ps *requested_state = ni_get_ps(rdev->pm.dpm.requested_ps); + struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); + struct ni_ps *requested_state = ni_get_ps(&eg_pi->requested_rps); if (low) return requested_state->performance_levels[0].sclk; @@ -4088,7 +4130,8 @@ u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low) u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low) { - struct ni_ps *requested_state = ni_get_ps(rdev->pm.dpm.requested_ps); + struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); + struct ni_ps *requested_state = ni_get_ps(&eg_pi->requested_rps); if (low) return requested_state->performance_levels[0].mclk; diff --git a/drivers/gpu/drm/radeon/ni_dpm.h b/drivers/gpu/drm/radeon/ni_dpm.h index e10f747..59c1692 100644 --- a/drivers/gpu/drm/radeon/ni_dpm.h +++ b/drivers/gpu/drm/radeon/ni_dpm.h @@ -202,7 +202,8 @@ struct ni_power_info { const struct ni_cac_weights *cac_weights; u8 lta_window_size; u8 lts_truncate; - struct ni_ps hw_ps; + struct ni_ps current_ps; + struct ni_ps requested_ps; /* scratch structs */ SMC_NIslands_MCRegisters smc_mc_reg_table; NISLANDS_SMC_STATETABLE smc_statetable; diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c index 25eeaa4..e7162b1 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.c +++ b/drivers/gpu/drm/radeon/radeon_asic.c @@ -1821,7 +1821,9 @@ static struct radeon_asic cayman_asic = { .setup_asic = &ni_dpm_setup_asic, .enable = &ni_dpm_enable, .disable = &ni_dpm_disable, + .pre_set_power_state = &ni_dpm_pre_set_power_state, .set_power_state = &ni_dpm_set_power_state, + .post_set_power_state = &ni_dpm_post_set_power_state, .display_configuration_changed = &cypress_dpm_display_configuration_changed, .fini = &ni_dpm_fini, .get_sclk = &ni_dpm_get_sclk, diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h index 696d6e9..7b898bc 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.h +++ b/drivers/gpu/drm/radeon/radeon_asic.h @@ -593,7 +593,9 @@ int ni_dpm_init(struct radeon_device *rdev); void ni_dpm_setup_asic(struct radeon_device *rdev); int ni_dpm_enable(struct radeon_device *rdev); void ni_dpm_disable(struct radeon_device *rdev); +int ni_dpm_pre_set_power_state(struct radeon_device *rdev); int ni_dpm_set_power_state(struct radeon_device *rdev); +void ni_dpm_post_set_power_state(struct radeon_device *rdev); void ni_dpm_fini(struct radeon_device *rdev); u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low); u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low);