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[74.96.105.49]) by mx.google.com with ESMTPSA id r10sm32665096qeu.4.2013.06.26.06.25.30 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 26 Jun 2013 06:25:30 -0700 (PDT) From: alexdeucher@gmail.com To: dri-devel@lists.freedesktop.org Subject: [PATCH 111/165] drm/radeon/dpm: remove local sumo_get_xclk() Date: Wed, 26 Jun 2013 09:23:11 -0400 Message-Id: <1372253045-17042-112-git-send-email-alexdeucher@gmail.com> X-Mailer: git-send-email 1.7.7.5 In-Reply-To: <1372253045-17042-1-git-send-email-alexdeucher@gmail.com> References: <1372253045-17042-1-git-send-email-alexdeucher@gmail.com> Cc: Alex Deucher X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org Errors-To: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Alex Deucher Use the new asic callback instead. Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/sumo_dpm.c | 19 +++++++------------ drivers/gpu/drm/radeon/sumo_dpm.h | 1 - drivers/gpu/drm/radeon/sumo_smc.c | 2 +- drivers/gpu/drm/radeon/trinity_dpm.c | 6 +++--- 4 files changed, 11 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/radeon/sumo_dpm.c b/drivers/gpu/drm/radeon/sumo_dpm.c index 10700e1..80fb3ac 100644 --- a/drivers/gpu/drm/radeon/sumo_dpm.c +++ b/drivers/gpu/drm/radeon/sumo_dpm.c @@ -84,11 +84,6 @@ struct sumo_power_info *sumo_get_pi(struct radeon_device *rdev) return pi; } -u32 sumo_get_xclk(struct radeon_device *rdev) -{ - return rdev->clock.spll.reference_freq; -} - static void sumo_gfx_clockgating_enable(struct radeon_device *rdev, bool enable) { if (enable) @@ -124,7 +119,7 @@ static void sumo_mg_clockgating_enable(struct radeon_device *rdev, bool enable) static void sumo_program_git(struct radeon_device *rdev) { u32 p, u; - u32 xclk = sumo_get_xclk(rdev); + u32 xclk = radeon_get_xclk(rdev); r600_calculate_u_and_p(SUMO_GICST_DFLT, xclk, 16, &p, &u); @@ -135,7 +130,7 @@ static void sumo_program_git(struct radeon_device *rdev) static void sumo_program_grsd(struct radeon_device *rdev) { u32 p, u; - u32 xclk = sumo_get_xclk(rdev); + u32 xclk = radeon_get_xclk(rdev); u32 grs = 256 * 25 / 100; r600_calculate_u_and_p(1, xclk, 14, &p, &u); @@ -155,7 +150,7 @@ static void sumo_gfx_powergating_initialize(struct radeon_device *rdev) u32 p, u; u32 p_c, p_p, d_p; u32 r_t, i_t; - u32 xclk = sumo_get_xclk(rdev); + u32 xclk = radeon_get_xclk(rdev); if (rdev->family == CHIP_PALM) { p_c = 4; @@ -319,7 +314,7 @@ static void sumo_calculate_bsp(struct radeon_device *rdev, u32 high_clk) { struct sumo_power_info *pi = sumo_get_pi(rdev); - u32 xclk = sumo_get_xclk(rdev); + u32 xclk = radeon_get_xclk(rdev); pi->pasi = 65535 * 100 / high_clk; pi->asi = 65535 * 100 / high_clk; @@ -466,7 +461,7 @@ void sumo_clear_vc(struct radeon_device *rdev) void sumo_program_sstp(struct radeon_device *rdev) { u32 p, u; - u32 xclk = sumo_get_xclk(rdev); + u32 xclk = radeon_get_xclk(rdev); r600_calculate_u_and_p(SUMO_SST_DFLT, xclk, 16, &p, &u); @@ -909,7 +904,7 @@ static void sumo_start_am(struct radeon_device *rdev) static void sumo_program_ttp(struct radeon_device *rdev) { - u32 xclk = sumo_get_xclk(rdev); + u32 xclk = radeon_get_xclk(rdev); u32 p, u; u32 cg_sclk_dpm_ctrl_5 = RREG32(CG_SCLK_DPM_CTRL_5); @@ -955,7 +950,7 @@ static void sumo_program_dc_hto(struct radeon_device *rdev) { u32 cg_sclk_dpm_ctrl_4 = RREG32(CG_SCLK_DPM_CTRL_4); u32 p, u; - u32 xclk = sumo_get_xclk(rdev); + u32 xclk = radeon_get_xclk(rdev); r600_calculate_u_and_p(100000, xclk, 14, &p, &u); diff --git a/drivers/gpu/drm/radeon/sumo_dpm.h b/drivers/gpu/drm/radeon/sumo_dpm.h index a3a7a61..07dda29 100644 --- a/drivers/gpu/drm/radeon/sumo_dpm.h +++ b/drivers/gpu/drm/radeon/sumo_dpm.h @@ -188,7 +188,6 @@ struct sumo_power_info { #define SUMO_GFXPOWERGATINGT_DFLT 100 /* sumo_dpm.c */ -u32 sumo_get_xclk(struct radeon_device *rdev); void sumo_gfx_clockgating_initialize(struct radeon_device *rdev); void sumo_program_vc(struct radeon_device *rdev, u32 vrc); void sumo_clear_vc(struct radeon_device *rdev); diff --git a/drivers/gpu/drm/radeon/sumo_smc.c b/drivers/gpu/drm/radeon/sumo_smc.c index bc1a510..9cbf0b2 100644 --- a/drivers/gpu/drm/radeon/sumo_smc.c +++ b/drivers/gpu/drm/radeon/sumo_smc.c @@ -146,7 +146,7 @@ void sumo_enable_boost_timer(struct radeon_device *rdev) { struct sumo_power_info *pi = sumo_get_pi(rdev); u32 period, unit, timer_value; - u32 xclk = sumo_get_xclk(rdev); + u32 xclk = radeon_get_xclk(rdev); unit = (RREG32_RCU(RCU_LCLK_SCALING_CNTL) & LCLK_SCALING_TIMER_PRESCALER_MASK) >> LCLK_SCALING_TIMER_PRESCALER_SHIFT; diff --git a/drivers/gpu/drm/radeon/trinity_dpm.c b/drivers/gpu/drm/radeon/trinity_dpm.c index 1699e93..b2dc905 100644 --- a/drivers/gpu/drm/radeon/trinity_dpm.c +++ b/drivers/gpu/drm/radeon/trinity_dpm.c @@ -361,7 +361,7 @@ static void trinity_gfx_powergating_initialize(struct radeon_device *rdev) u32 p, u; u32 value; struct atom_clock_dividers dividers; - u32 xclk = sumo_get_xclk(rdev); + u32 xclk = radeon_get_xclk(rdev); u32 sssd = 1; int ret; u32 hw_rev = (RREG32(HW_REV) & ATI_REV_ID_MASK) >> ATI_REV_ID_SHIFT; @@ -880,7 +880,7 @@ static void trinity_setup_uvd_dpm_interval(struct radeon_device *rdev, u32 p, u; u32 tp = RREG32_SMC(PM_TP); u32 val; - u32 xclk = sumo_get_xclk(rdev); + u32 xclk = radeon_get_xclk(rdev); r600_calculate_u_and_p(interval, xclk, 16, &p, &u); @@ -1000,7 +1000,7 @@ static void trinity_program_sclk_dpm(struct radeon_device *rdev) u32 p, u; u32 tp = RREG32_SMC(PM_TP); u32 ni; - u32 xclk = sumo_get_xclk(rdev); + u32 xclk = radeon_get_xclk(rdev); u32 value; r600_calculate_u_and_p(400, xclk, 16, &p, &u);