r600g, radeonsi: set/get the scanout flag using the set/get_tiling ioctls

Message ID	1376331250-32665-1-git-send-email-marek.olsak@amd.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org> From: "=?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?=" <maraeo@gmail.com> To: mesa-dev@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH] r600g, radeonsi: set/get the scanout flag using the set/get_tiling ioctls Date: Mon, 12 Aug 2013 20:14:10 +0200 Message-Id: <1376331250-32665-1-git-send-email-marek.olsak@amd.com> Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org Errors-To: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org

diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c index e69a605..dad3dc5 100644 --- a/src/gallium/drivers/r300/r300_state.c +++ b/src/gallium/drivers/r300/r300_state.c @@ -843,7 +843,7 @@ static void r300_tex_set_tiling_flags(struct r300_context *r300, tex->tex.macrotile[level]) { r300->rws->buffer_set_tiling(tex->buf, r300->cs, tex->tex.microtile, tex->tex.macrotile[level], - 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, FALSE, tex->tex.stride_in_bytes[0]); tex->surface_level = level; diff --git a/src/gallium/drivers/r300/r300_texture.c b/src/gallium/drivers/r300/r300_texture.c index 13e9bc3..4b58f06 100644 --- a/src/gallium/drivers/r300/r300_texture.c +++ b/src/gallium/drivers/r300/r300_texture.c @@ -1059,7 +1059,7 @@ r300_texture_create_object(struct r300_screen *rscreen, rws->buffer_set_tiling(tex->buf, NULL, tex->tex.microtile, tex->tex.macrotile[0], - 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, FALSE, tex->tex.stride_in_bytes[0]); return tex; @@ -1115,7 +1115,7 @@ struct pipe_resource *r300_texture_from_handle(struct pipe_screen *screen, if (!buffer) return NULL; - rws->buffer_get_tiling(buffer, &microtile, &macrotile, NULL, NULL, NULL, NULL, NULL); + rws->buffer_get_tiling(buffer, &microtile, &macrotile, NULL, NULL, NULL, NULL, NULL, NULL); /* Enforce a microtiled zbuffer. */ if (util_format_is_depth_or_stencil(base->format) && diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c index 742e982..f27d0dc 100644 --- a/src/gallium/drivers/r600/r600_texture.c +++ b/src/gallium/drivers/r600/r600_texture.c @@ -131,7 +131,7 @@ static int r600_init_surface(struct r600_screen *rscreen, struct radeon_surface *surface, const struct pipe_resource *ptex, unsigned array_mode, - bool is_flushed_depth) + bool is_flushed_depth, bool is_scanout) { const struct util_format_description *desc = util_format_description(ptex->format); @@ -205,7 +205,7 @@ static int r600_init_surface(struct r600_screen *rscreen, default: return -EINVAL; } - if (ptex->bind & PIPE_BIND_SCANOUT) { + if (is_scanout) { surface->flags |= RADEON_SURF_SCANOUT; } @@ -285,6 +285,7 @@ static boolean r600_texture_get_handle(struct pipe_screen* screen, surface->tile_split, surface->stencil_tile_split, surface->mtilea, + (surface->flags & RADEON_SURF_SCANOUT) != 0, rtex->surface.level[0].pitch_bytes); return rscreen->ws->buffer_get_handle(resource->buf, @@ -624,7 +625,8 @@ struct pipe_resource *r600_texture_create(struct pipe_screen *screen, } r = r600_init_surface(rscreen, &surface, templ, array_mode, - templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH); + (templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH) != 0, + (templ->bind & PIPE_BIND_SCANOUT) != 0); if (r) { return NULL; } @@ -689,6 +691,7 @@ struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen, unsigned array_mode = 0; enum radeon_bo_layout micro, macro; struct radeon_surface surface; + boolean scanout; int r; /* Support only 2D textures without mipmaps */ @@ -704,7 +707,7 @@ struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen, &surface.bankw, &surface.bankh, &surface.tile_split, &surface.stencil_tile_split, - &surface.mtilea); + &surface.mtilea, &scanout); if (macro == RADEON_LAYOUT_TILED) array_mode = V_0280A0_ARRAY_2D_TILED_THIN1; @@ -713,7 +716,7 @@ struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen, else array_mode = V_038000_ARRAY_LINEAR_ALIGNED; - r = r600_init_surface(rscreen, &surface, templ, array_mode, false); + r = r600_init_surface(rscreen, &surface, templ, array_mode, false, scanout); if (r) { return NULL; } diff --git a/src/gallium/drivers/radeonsi/r600_texture.c b/src/gallium/drivers/radeonsi/r600_texture.c index 8e01b14..8841cea 100644 --- a/src/gallium/drivers/radeonsi/r600_texture.c +++ b/src/gallium/drivers/radeonsi/r600_texture.c @@ -124,7 +124,7 @@ static int r600_init_surface(struct r600_screen *rscreen, struct radeon_surface *surface, const struct pipe_resource *ptex, unsigned array_mode, - bool is_flushed_depth) + bool is_flushed_depth, bool is_scanout) { const struct util_format_description *desc = util_format_description(ptex->format); @@ -197,7 +197,7 @@ static int r600_init_surface(struct r600_screen *rscreen, default: return -EINVAL; } - if (ptex->bind & PIPE_BIND_SCANOUT) { + if (is_scanout) { surface->flags |= RADEON_SURF_SCANOUT; } @@ -260,6 +260,7 @@ static boolean r600_texture_get_handle(struct pipe_screen* screen, surface->tile_split, surface->stencil_tile_split, surface->mtilea, + (surface->flags & RADEON_SURF_SCANOUT) != 0, surface->level[0].pitch_bytes); return rscreen->ws->buffer_get_handle(resource->buf, @@ -534,7 +535,8 @@ struct pipe_resource *si_texture_create(struct pipe_screen *screen, } r = r600_init_surface(rscreen, &surface, templ, array_mode, - templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH); + (templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH) != 0, + (templ->bind & PIPE_BIND_SCANOUT) != 0); if (r) { return NULL; } @@ -592,6 +594,7 @@ struct pipe_resource *si_texture_from_handle(struct pipe_screen *screen, unsigned array_mode; enum radeon_bo_layout micro, macro; struct radeon_surface surface; + boolean scanout; int r; /* Support only 2D textures without mipmaps */ @@ -607,7 +610,7 @@ struct pipe_resource *si_texture_from_handle(struct pipe_screen *screen, &surface.bankw, &surface.bankh, &surface.tile_split, &surface.stencil_tile_split, - &surface.mtilea); + &surface.mtilea, &scanout); if (macro == RADEON_LAYOUT_TILED) array_mode = V_009910_ARRAY_2D_TILED_THIN1; @@ -616,7 +619,7 @@ struct pipe_resource *si_texture_from_handle(struct pipe_screen *screen, else array_mode = V_009910_ARRAY_LINEAR_ALIGNED; - r = r600_init_surface(rscreen, &surface, templ, array_mode, false); + r = r600_init_surface(rscreen, &surface, templ, array_mode, false, scanout); if (r) { return NULL; } diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c index 19e2715..1b3573b 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c @@ -48,6 +48,7 @@ */ #define RADEON_BO_FLAGS_MACRO_TILE 1 #define RADEON_BO_FLAGS_MICRO_TILE 2 +#define RADEON_TILING_R600_SCANOUT 0x4 /* r600 and later */ #define RADEON_BO_FLAGS_MICRO_TILE_SQUARE 0x20 #ifndef DRM_RADEON_GEM_WAIT @@ -738,7 +739,8 @@ static void radeon_bo_get_tiling(struct pb_buffer *_buf, unsigned *bankw, unsigned *bankh, unsigned *tile_split, unsigned *stencil_tile_split, - unsigned *mtilea) + unsigned *mtilea, + boolean *scanout) { struct radeon_bo *bo = get_radeon_bo(_buf); struct drm_radeon_gem_set_tiling args; @@ -759,13 +761,14 @@ static void radeon_bo_get_tiling(struct pb_buffer *_buf, if (args.tiling_flags & RADEON_BO_FLAGS_MACRO_TILE) *macrotiled = RADEON_LAYOUT_TILED; - if (bankw && tile_split && stencil_tile_split && mtilea && tile_split) { + if (bankw && tile_split && stencil_tile_split && mtilea && tile_split && scanout) { *bankw = (args.tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; *bankh = (args.tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; *tile_split = (args.tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; *stencil_tile_split = (args.tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK; *mtilea = (args.tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; *tile_split = eg_tile_split(*tile_split); + *scanout = (args.tiling_flags & RADEON_TILING_R600_SCANOUT) != 0; } } @@ -777,6 +780,7 @@ static void radeon_bo_set_tiling(struct pb_buffer *_buf, unsigned tile_split, unsigned stencil_tile_split, unsigned mtilea, + boolean scanout, uint32_t pitch) { struct radeon_bo *bo = get_radeon_bo(_buf); @@ -818,6 +822,10 @@ static void radeon_bo_set_tiling(struct pb_buffer *_buf, args.tiling_flags |= (mtilea & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK) << RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT; + if (cs->ws->gen >= DRV_R600 && scanout) { + args.tiling_flags |= RADEON_TILING_R600_SCANOUT; + } + args.handle = bo->handle; args.pitch = pitch; diff --git a/src/gallium/winsys/radeon/drm/radeon_winsys.h b/src/gallium/winsys/radeon/drm/radeon_winsys.h index a619d70..fb95848 100644 --- a/src/gallium/winsys/radeon/drm/radeon_winsys.h +++ b/src/gallium/winsys/radeon/drm/radeon_winsys.h @@ -305,7 +305,8 @@ struct radeon_winsys { unsigned *bankw, unsigned *bankh, unsigned *tile_split, unsigned *stencil_tile_split, - unsigned *mtilea); + unsigned *mtilea, + boolean *scanout); /** * Set tiling flags describing a memory layout of a buffer object. @@ -326,6 +327,7 @@ struct radeon_winsys { unsigned tile_split, unsigned stencil_tile_split, unsigned mtilea, + boolean scanout, unsigned stride); /**

r600g, radeonsi: set/get the scanout flag using the set/get_tiling ioctls

Commit Message

Patch