From patchwork Tue Aug 13 08:14:19 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shirish S X-Patchwork-Id: 2843755 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 4C0B4BF546 for ; Tue, 13 Aug 2013 15:17:05 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8E2462039D for ; Tue, 13 Aug 2013 15:17:00 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 515C420373 for ; Tue, 13 Aug 2013 15:16:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3567CE7588 for ; Tue, 13 Aug 2013 08:16:59 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mailout1.samsung.com (mailout1.samsung.com [203.254.224.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 45549E789C for ; Tue, 13 Aug 2013 00:52:12 -0700 (PDT) Received: from epcpsbgr5.samsung.com (u145.gpu120.samsung.co.kr [203.254.230.145]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MRG00JOALUQENI0@mailout1.samsung.com> for dri-devel@lists.freedesktop.org; Tue, 13 Aug 2013 16:52:05 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.124]) by epcpsbgr5.samsung.com (EPCPMTA) with SMTP id D9.25.11618.5A5E9025; Tue, 13 Aug 2013 16:52:05 +0900 (KST) X-AuditID: cbfee691-b7fef6d000002d62-78-5209e5a53cdc Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id EC.A9.32250.5A5E9025; Tue, 13 Aug 2013 16:52:05 +0900 (KST) Received: from chromeserver-PowerEdge-T410.sisodomain.com ([107.108.73.106]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MRG00K7WLUMS6D0@mmp1.samsung.com>; Tue, 13 Aug 2013 16:52:05 +0900 (KST) From: Shirish S To: dri-devel@lists.freedesktop.org, inki.dae@samsung.com Subject: [PATCH 1/3] ARM: dts: smdk5250: Add hdmi phy settings Date: Tue, 13 Aug 2013 13:44:19 +0530 Message-id: <1376381661-28847-2-git-send-email-s.shirish@samsung.com> X-Mailer: git-send-email 1.7.10.4 In-reply-to: <1376381661-28847-1-git-send-email-s.shirish@samsung.com> References: <1376381661-28847-1-git-send-email-s.shirish@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrILMWRmVeSWpSXmKPExsWyRsSkRnfpU84gg023VC16z51ksrjy9T2b xaT7E1gsmnYcZHNg8ZjdcJHFY/u3B6we97uPM3n0bVnFGMASxWWTkpqTWZZapG+XwJXxZvl/ toL7ShV3t+5iamBcIdHFyMkhIWAi8er1NHYIW0ziwr31bF2MXBxCAksZJWaf28UKU3Tzy3kW iMQiRon7bxexgCSEBGYzSVybFARiswmoS1ycvJoZxBYRsJR4sPU3mM0soCXxaC/EIGEBO4lH DTfAbBYBVYl1f04BbePg4BVwlbj3VA1il6JE97MJbCA2p4CbxNpPS8FKhIBKVmzUBTlBQuA/ m8T5cxtZIMYISHybfIgFpEZCQFZi0wFmiDGSEgdX3GCZwCi8gJFhFaNoakFyQXFSepGpXnFi bnFpXrpecn7uJkZg8J7+92ziDsb7B6wPMSYDjZvILCWanA8M/rySeENjMyMLUxNTYyNzSzPS hJXEedVbrAOFBNITS1KzU1MLUovii0pzUosPMTJxcEo1MO6Wl63hS4+5qWTNInkz6qFVbYHV E9fzC1o+sQY5af9PDt694HaEzYsbP7xNFh389HXv//jtWhXXDz5vK2u1LVz4edub0ypKoRpm bd4X5ifHfDYVLDHOUxO8YxXbcPrjT+sAtz57j2UtnJv2HeOdGvPHT/FpgIfC5bR7/CfuHmwL 226S63Y8UYmlOCPRUIu5qDgRAJXCLkR0AgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrHIsWRmVeSWpSXmKPExsVy+t9jAd2lTzmDDNqmyVn0njvJZHHl63s2 i0n3J7BYNO04yObA4jG74SKLx/ZvD1g97ncfZ/Lo27KKMYAlqoHRJiM1MSW1SCE1Lzk/JTMv 3VbJOzjeOd7UzMBQ19DSwlxJIS8xN9VWycUnQNctMwdoqZJCWWJOKVAoILG4WEnfDtOE0BA3 XQuYxghd35AguB4jAzSQsIYx483y/2wF95Uq7m7dxdTAuEKii5GTQ0LAROLml/MsELaYxIV7 69m6GLk4hAQWMUrcf7sILCEkMJtJ4tqkIBCbTUBd4uLk1cwgtoiApcSDrb/BbGYBLYlHe3ex gtjCAnYSjxpugNksAqoS6/6cAhrKwcEr4Cpx76kaxC5Fie5nE9hAbE4BN4m1n5aClQgBlazY qDuBkXcBI8MqRtHUguSC4qT0XEO94sTc4tK8dL3k/NxNjODYeCa1g3Flg8UhRgEORiUeXoH3 HEFCrIllxZW5hxglOJiVRHhP6nAGCfGmJFZWpRblxxeV5qQWH2JMBrppIrOUaHI+MG7zSuIN jU3MTY1NLU0sTMwsSRNWEuc90GodKCSQnliSmp2aWpBaBLOFiYNTqoGxbZHEq5XRLK9050x0 vmo46ZDLJ86l6Qa67NcqjDW6XzwTvqkgo+MfntlyYqr4N/v/f//Mi1XZ+GzS6Z0aLzeeznFp Xvkka+ql+8w8PelravxrtFLElgnKJL3265rmqvnr0kRtv8D7xyb6XZ8Sdy3WtjSv8Ht9SLPn IYfGK31SixOOzL9dOem+EktxRqKhFnNRcSIAEe1IvtECAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-Mailman-Approved-At: Tue, 13 Aug 2013 08:09:57 -0700 Cc: shirish@chromium.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org Errors-To: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org X-Spam-Status: No, score=-7.0 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch moves the hdmi phy setting to smdk5250 dts,as its more of a per board configuration and also shall be easier for supporting future chipsets. Signed-off-by: Shirish S --- arch/arm/boot/dts/exynos5250-smdk5250.dts | 120 +++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 49f18c2..95a91a8 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -220,6 +220,126 @@ hdmi { hpd-gpio = <&gpx3 7 0>; + hdmiphy_confs { + nr_confs = <13>; + conf0: conf0 { + clock-frequency = <25200000>; + conf = /bits/ 8 < + 0x01 0x51 0x2A 0x75 0x40 0x01 0x00 0x08 + 0x82 0x80 0xfc 0xd8 0x45 0xa0 0xac 0x80 + 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86 + 0x54 0xf4 0x24 0x00 0x00 0x00 0x01 0x80 + >; + }; + conf1: conf1 { + clock-frequency = <27000000>; + conf = /bits/ 8 < + 0x01 0xd1 0x22 0x51 0x40 0x08 0xfc 0x20 + 0x98 0xa0 0xcb 0xd8 0x45 0xa0 0xac 0x80 + 0x06 0x80 0x11 0x04 0x02 0x22 0x44 0x86 + 0x54 0xe4 0x24 0x00 0x00 0x00 0x01 0x80 + >; + }; + conf2: conf2 { + clock-frequency = <27027000>; + conf = /bits/ 8 < + 0x01 0xd1 0x2d 0x72 0x40 0x64 0x12 0x08 + 0x43 0xa0 0x0e 0xd9 0x45 0xa0 0xac 0x80 + 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86 + 0x54 0xe3 0x24 0x00 0x00 0x00 0x01 0x00 + >; + }; + conf3: conf3 { + clock-frequency = <36000000>; + conf = /bits/ 8 < + 0x01 0x51 0x2d 0x55 0x40 0x01 0x00 0x08 + 0x82 0x80 0x0e 0xd9 0x45 0xa0 0xac 0x80 + 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86 + 0x54 0xab 0x24 0x00 0x00 0x00 0x01 0x80 + >; + }; + conf4: conf4 { + clock-frequency = <40000000>; + conf = /bits/ 8 < + 0x01 0x51 0x32 0x55 0x40 0x01 0x00 0x08 + 0x82 0x80 0x2c 0xd9 0x45 0xa0 0xac 0x80 + 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86 + 0x54 0x9a 0x24 0x00 0x00 0x00 0x01 0x80 + >; + }; + conf5: conf5 { + clock-frequency = <65000000>; + conf = /bits/ 8 < + 0x01 0xd1 0x36 0x34 0x40 0x1e 0x0a 0x08 + 0x82 0xa0 0x45 0xd9 0x45 0xa0 0xac 0x80 + 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86 + 0x54 0xbd 0x24 0x01 0x00 0x00 0x01 0x80 + >; + }; + conf6: conf6 { + clock-frequency = <74176000>; + conf = /bits/ 8 < + 0x01 0xd1 0x3e 0x35 0x40 0x5b 0xde 0x08 + 0x82 0xa0 0x73 0xd9 0x45 0xa0 0xac 0x80 + 0x56 0x80 0x11 0x04 0x02 0x22 0x44 0x86 + 0x54 0xa6 0x24 0x01 0x00 0x00 0x01 0x80 + >; + }; + conf7: conf7 { + clock-frequency = <74250000>; + conf = /bits/ 8 < + 0x01 0xd1 0x1f 0x10 0x40 0x40 0xf8 0x08 + 0x81 0xa0 0xba 0xd8 0x45 0xa0 0xac 0x80 + 0x3c 0x80 0x11 0x04 0x02 0x22 0x44 0x86 + 0x54 0xa5 0x24 0x01 0x00 0x00 0x01 0x00 + >; + }; + conf8: conf8 { + clock-frequency = <83500000>; + conf = /bits/ 8 < + 0x01 0xd1 0x23 0x11 0x40 0x0c 0xfb 0x08 + 0x85 0xa0 0xd1 0xd8 0x45 0xa0 0xac 0x80 + 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86 + 0x54 0x93 0x24 0x01 0x00 0x00 0x01 0x80 + >; + }; + conf9: conf9 { + clock-frequency = <106500000>; + conf = /bits/ 8 < + 0x01 0xd1 0x2c 0x12 0x40 0x0c 0x09 0x08 + 0x84 0xa0 0x0a 0xd9 0x45 0xa0 0xac 0x80 + 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86 + 0x54 0x73 0x24 0x01 0x00 0x00 0x01 0x80 + >; + }; + conf10: conf10 { + clock-frequency = <108000000>; + conf = /bits/ 8 < + 0x01 0x51 0x2d 0x15 0x40 0x01 0x00 0x08 + 0x82 0x80 0x0e 0xd9 0x45 0xa0 0xac 0x80 + 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86 + 0x54 0xc7 0x25 0x03 0x00 0x00 0x01 0x80 + >; + }; + conf11: conf11 { + clock-frequency = <146250000>; + conf = /bits/ 8 < + 0x01 0xd1 0x3d 0x15 0x40 0x18 0xfd 0x08 + 0x83 0xa0 0x6e 0xd9 0x45 0xa0 0xac 0x80 + 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86 + 0x54 0x50 0x25 0x03 0x00 0x00 0x01 0x80 + >; + }; + conf12: conf12 { + clock-frequency = <148500000>; + conf = /bits/ 8 < + 0x01 0xd1 0x1f 0x00 0x40 0x40 0xf8 0x08 + 0x81 0xa0 0xba 0xd8 0x45 0xa0 0xac 0x80 + 0x3c 0x80 0x11 0x04 0x02 0x22 0x44 0x86 + 0x54 0x4b 0x25 0x03 0x00 0x00 0x01 0x00 + >; + }; + }; }; codec@11000000 {