From patchwork Tue Aug 13 08:14:20 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shirish S X-Patchwork-Id: 2843754 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 13A49BF546 for ; Tue, 13 Aug 2013 15:14:41 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C2DBE2050B for ; Tue, 13 Aug 2013 15:14:39 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 89FE0204FC for ; Tue, 13 Aug 2013 15:14:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 73443E79EA for ; Tue, 13 Aug 2013 08:14:38 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mailout2.samsung.com (mailout2.samsung.com [203.254.224.25]) by gabe.freedesktop.org (Postfix) with ESMTP id E0016E7880 for ; Tue, 13 Aug 2013 00:52:08 -0700 (PDT) Received: from epcpsbgr4.samsung.com (u144.gpu120.samsung.co.kr [203.254.230.144]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MRG00KJTLTU4XO0@mailout2.samsung.com> for dri-devel@lists.freedesktop.org; Tue, 13 Aug 2013 16:52:06 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.122]) by epcpsbgr4.samsung.com (EPCPMTA) with SMTP id 9B.44.29708.6A5E9025; Tue, 13 Aug 2013 16:52:06 +0900 (KST) X-AuditID: cbfee690-b7f6f6d00000740c-5c-5209e5a63b95 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id DB.B9.31505.6A5E9025; Tue, 13 Aug 2013 16:52:06 +0900 (KST) Received: from chromeserver-PowerEdge-T410.sisodomain.com ([107.108.73.106]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MRG00K7WLUMS6D0@mmp1.samsung.com>; Tue, 13 Aug 2013 16:52:06 +0900 (KST) From: Shirish S To: dri-devel@lists.freedesktop.org, inki.dae@samsung.com Subject: [PATCH 2/3] ARM: dts: arndale: Add hdmi phy settings Date: Tue, 13 Aug 2013 13:44:20 +0530 Message-id: <1376381661-28847-3-git-send-email-s.shirish@samsung.com> X-Mailer: git-send-email 1.7.10.4 In-reply-to: <1376381661-28847-1-git-send-email-s.shirish@samsung.com> References: <1376381661-28847-1-git-send-email-s.shirish@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrELMWRmVeSWpSXmKPExsWyRsSkSnfZU84gg6cfFSx6z51ksrjy9T2b xaT7E1gsmnYcZHNg8ZjdcJHFY/u3B6we97uPM3n0bVnFGMASxWWTkpqTWZZapG+XwJWx6WRq wULlinUTdjE2MD6Q6GLk5JAQMJE4820aE4QtJnHh3nq2LkYuDiGBpYwSs/b/ZIcp6r07jx0i sYhRYt/dn4wQzmwmiS1Nk1hAqtgE1CUuTl7NDGKLCFhKPNj6G8xmFtCSeLR3FyuILSxgJ7H+ /UywdSwCqhI3N58Ei/MKuEo829nNBrFNUaL72QQwm1PATWLtp6VANgfQMleJFRt1QfZKCPxn k/i89TIzxBwBiW+TD7GA1EgIyEpsOsAMMUZS4uCKGywTGIUXMDKsYhRNLUguKE5KLzLRK07M LS7NS9dLzs/dxAgM39P/nk3YwXjvgPUhxmSgcROZpUST84Hhn1cSb2hsZmRhamJqbGRuaUaa sJI4r3qLdaCQQHpiSWp2ampBalF8UWlOavEhRiYOTqkGxvrb03KXT874HhYYEf/mu1T2yfTO nOOvbF5sEW+d+r/yV/+Wk5LzJr6568uhdaP6ys0Sd5WOSwrz7xVeNPou5HZYYU5z9G7rWV77 pNJZuv6Jz07ZF3+Zuz3BqX/ppr+mrpwZV88p/S4QX5iXuEi25ZjdVdN59wNYJNbZLpqVJTZh 94ftk/13dSixFGckGmoxFxUnAgATg6X+dQIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrPIsWRmVeSWpSXmKPExsVy+t9jAd1lTzmDDE73S1j0njvJZHHl63s2 i0n3J7BYNO04yObA4jG74SKLx/ZvD1g97ncfZ/Lo27KKMYAlqoHRJiM1MSW1SCE1Lzk/JTMv 3VbJOzjeOd7UzMBQ19DSwlxJIS8xN9VWycUnQNctMwdoqZJCWWJOKVAoILG4WEnfDtOE0BA3 XQuYxghd35AguB4jAzSQsIYxY9PJ1IKFyhXrJuxibGB8INHFyMkhIWAi0Xt3HjuELSZx4d56 ti5GLg4hgUWMEvvu/mSEcGYzSWxpmsQCUsUmoC5xcfJqZhBbRMBS4sHW32A2s4CWxKO9u1hB bGEBO4n172cygdgsAqoSNzefBIvzCrhKPNvZzQaxTVGi+9kEMJtTwE1i7aelQDYH0DJXiRUb dScw8i5gZFjFKJpakFxQnJSea6RXnJhbXJqXrpecn7uJERwdz6R3MK5qsDjEKMDBqMTDm/GR I0iINbGsuDL3EKMEB7OSCO9JHc4gId6UxMqq1KL8+KLSnNTiQ4zJQEdNZJYSTc4HRm5eSbyh sYm5qbGppYmFiZklacJK4rwHW60DhQTSE0tSs1NTC1KLYLYwcXBKNTDKfN3v//C43stHl/dI BNX7XAgsjWJPCj+u5bTjq2i+zTrVZwtLNvGJXXNo+bFp7sOsj1pcgU2xr9YVxrWcPNscUFWe /Mf14iUn3nu34nWvGvCqpUby6x3u43kQw7fQ/PTlgwymzPNv3X56s+kwT4NAdPutZe6qfBLL ud77v/47aWJ2CUPmGUclluKMREMt5qLiRABnKPrt0gIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-Mailman-Approved-At: Tue, 13 Aug 2013 08:09:56 -0700 Cc: shirish@chromium.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org Errors-To: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org X-Spam-Status: No, score=-7.0 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch moves the hdmi phy setting to arndale dts, as its more of a per board configuration and also shall be easier for supporting future chipsets. Signed-off-by: Shirish S --- arch/arm/boot/dts/exynos5250-arndale.dts | 120 ++++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index abc7272..59db48a 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -424,6 +424,126 @@ hdmi { hpd-gpio = <&gpx3 7 2>; + hdmiphy_confs { + nr_confs = <13>; + conf0: conf0 { + clock-frequency = <25200000>; + conf = /bits/ 8 < + 0x01 0x51 0x2A 0x75 0x40 0x01 0x00 0x08 + 0x82 0x80 0xfc 0xd8 0x45 0xa0 0xac 0x80 + 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86 + 0x54 0xf4 0x24 0x00 0x00 0x00 0x01 0x80 + >; + }; + conf1: conf1 { + clock-frequency = <27000000>; + conf = /bits/ 8 < + 0x01 0xd1 0x22 0x51 0x40 0x08 0xfc 0x20 + 0x98 0xa0 0xcb 0xd8 0x45 0xa0 0xac 0x80 + 0x06 0x80 0x11 0x04 0x02 0x22 0x44 0x86 + 0x54 0xe4 0x24 0x00 0x00 0x00 0x01 0x80 + >; + }; + conf2: conf2 { + clock-frequency = <27027000>; + conf = /bits/ 8 < + 0x01 0xd1 0x2d 0x72 0x40 0x64 0x12 0x08 + 0x43 0xa0 0x0e 0xd9 0x45 0xa0 0xac 0x80 + 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86 + 0x54 0xe3 0x24 0x00 0x00 0x00 0x01 0x00 + >; + }; + conf3: conf3 { + clock-frequency = <36000000>; + conf = /bits/ 8 < + 0x01 0x51 0x2d 0x55 0x40 0x01 0x00 0x08 + 0x82 0x80 0x0e 0xd9 0x45 0xa0 0xac 0x80 + 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86 + 0x54 0xab 0x24 0x00 0x00 0x00 0x01 0x80 + >; + }; + conf4: conf4 { + clock-frequency = <40000000>; + conf = /bits/ 8 < + 0x01 0x51 0x32 0x55 0x40 0x01 0x00 0x08 + 0x82 0x80 0x2c 0xd9 0x45 0xa0 0xac 0x80 + 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86 + 0x54 0x9a 0x24 0x00 0x00 0x00 0x01 0x80 + >; + }; + conf5: conf5 { + clock-frequency = <65000000>; + conf = /bits/ 8 < + 0x01 0xd1 0x36 0x34 0x40 0x1e 0x0a 0x08 + 0x82 0xa0 0x45 0xd9 0x45 0xa0 0xac 0x80 + 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86 + 0x54 0xbd 0x24 0x01 0x00 0x00 0x01 0x80 + >; + }; + conf6: conf6 { + clock-frequency = <74176000>; + conf = /bits/ 8 < + 0x01 0xd1 0x3e 0x35 0x40 0x5b 0xde 0x08 + 0x82 0xa0 0x73 0xd9 0x45 0xa0 0xac 0x80 + 0x56 0x80 0x11 0x04 0x02 0x22 0x44 0x86 + 0x54 0xa6 0x24 0x01 0x00 0x00 0x01 0x80 + >; + }; + conf7: conf7 { + clock-frequency = <74250000>; + conf = /bits/ 8 < + 0x01 0xd1 0x1f 0x10 0x40 0x40 0xf8 0x08 + 0x81 0xa0 0xba 0xd8 0x45 0xa0 0xac 0x80 + 0x3c 0x80 0x11 0x04 0x02 0x22 0x44 0x86 + 0x54 0xa5 0x24 0x01 0x00 0x00 0x01 0x00 + >; + }; + conf8: conf8 { + clock-frequency = <83500000>; + conf = /bits/ 8 < + 0x01 0xd1 0x23 0x11 0x40 0x0c 0xfb 0x08 + 0x85 0xa0 0xd1 0xd8 0x45 0xa0 0xac 0x80 + 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86 + 0x54 0x93 0x24 0x01 0x00 0x00 0x01 0x80 + >; + }; + conf9: conf9 { + clock-frequency = <106500000>; + conf = /bits/ 8 < + 0x01 0xd1 0x2c 0x12 0x40 0x0c 0x09 0x08 + 0x84 0xa0 0x0a 0xd9 0x45 0xa0 0xac 0x80 + 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86 + 0x54 0x73 0x24 0x01 0x00 0x00 0x01 0x80 + >; + }; + conf10: conf10 { + clock-frequency = <108000000>; + conf = /bits/ 8 < + 0x01 0x51 0x2d 0x15 0x40 0x01 0x00 0x08 + 0x82 0x80 0x0e 0xd9 0x45 0xa0 0xac 0x80 + 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86 + 0x54 0xc7 0x25 0x03 0x00 0x00 0x01 0x80 + >; + }; + conf11: conf11 { + clock-frequency = <146250000>; + conf = /bits/ 8 < + 0x01 0xd1 0x3d 0x15 0x40 0x18 0xfd 0x08 + 0x83 0xa0 0x6e 0xd9 0x45 0xa0 0xac 0x80 + 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86 + 0x54 0x50 0x25 0x03 0x00 0x00 0x01 0x80 + >; + }; + conf12: conf12 { + clock-frequency = <148500000>; + conf = /bits/ 8 < + 0x01 0xd1 0x1f 0x00 0x40 0x40 0xf8 0x08 + 0x81 0xa0 0xba 0xd8 0x45 0xa0 0xac 0x80 + 0x3c 0x80 0x11 0x04 0x02 0x22 0x44 0x86 + 0x54 0x4b 0x25 0x03 0x00 0x00 0x01 0x00 + >; + }; + }; vdd_osc-supply = <&ldo10_reg>; vdd_pll-supply = <&ldo8_reg>; vdd-supply = <&ldo8_reg>;