From patchwork Wed Oct 2 22:09:12 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Deucher X-Patchwork-Id: 2978981 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 386089F245 for ; Wed, 2 Oct 2013 22:14:41 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7D02B202E6 for ; Wed, 2 Oct 2013 22:14:40 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id A5FEC200C1 for ; Wed, 2 Oct 2013 22:14:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7A8A7E7BE1 for ; Wed, 2 Oct 2013 15:14:39 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-qe0-f50.google.com (mail-qe0-f50.google.com [209.85.128.50]) by gabe.freedesktop.org (Postfix) with ESMTP id 4696BE7BAE for ; Wed, 2 Oct 2013 15:09:30 -0700 (PDT) Received: by mail-qe0-f50.google.com with SMTP id a11so1101079qen.37 for ; Wed, 02 Oct 2013 15:09:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=cpbhIbwYfhliT/ke96F03WFR9EyONfknsPl1BweuvdQ=; b=Sev6YthfBAYbJSRNiGBc9oFgzkSA0t+15dMxRoJexGb1UcZJ+GTGEkE4c7DLCHdx4f nc1PR078kuYQYch8UR1Gm9y4/PqKi+x/RcBTzrUZbkTM9gAsFiuaOXzH4ncTxiXqZiVT B25I0xv+RrFQQUjVAes2ugPH+sTJaYbUk1xdQEZcyny7PNpK0FQfKq7DFcVX6l1G6tLx ZFpx1+A80kwfKzviIvjmaKlT/2E7npmRTa7e7XhqKsGfczwxQOi3cZ7s/pZFRhJ7MiJ3 pjkrvRQAoKCciLLgdYG1/woC3n0UBUeftFigewvmiBBz6HaDs7GG47jAvtWtEV7M1fcN iVNA== X-Received: by 10.224.69.132 with SMTP id z4mr6422934qai.78.1380751769934; Wed, 02 Oct 2013 15:09:29 -0700 (PDT) Received: from localhost.localdomain (static-74-96-105-49.washdc.fios.verizon.net. [74.96.105.49]) by mx.google.com with ESMTPSA id x1sm9766372qai.6.1969.12.31.16.00.00 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Wed, 02 Oct 2013 15:09:29 -0700 (PDT) From: Alex Deucher To: dri-devel@lists.freedesktop.org Subject: [PATCH 1/2] drm/radeon: improve soft reset on SI Date: Wed, 2 Oct 2013 18:09:12 -0400 Message-Id: <1380751753-9186-1-git-send-email-alexander.deucher@amd.com> X-Mailer: git-send-email 1.8.3.1 Cc: Alex Deucher , stable@vger.kernel.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org Errors-To: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Disable CG/PG and stop the rlc before resetting. Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org --- drivers/gpu/drm/radeon/si.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index c354c10..d4652af 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c @@ -85,6 +85,9 @@ extern void si_dma_vm_set_page(struct radeon_device *rdev, uint32_t incr, uint32_t flags); static void si_enable_gui_idle_interrupt(struct radeon_device *rdev, bool enable); +static void si_fini_pg(struct radeon_device *rdev); +static void si_fini_cg(struct radeon_device *rdev); +static void si_rlc_stop(struct radeon_device *rdev); static const u32 verde_rlc_save_restore_register_list[] = { @@ -3608,6 +3611,13 @@ static void si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS)); + /* disable PG/CG */ + si_fini_pg(rdev); + si_fini_cg(rdev); + + /* stop the rlc */ + si_rlc_stop(rdev); + /* Disable CP parsing/prefetching */ WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);