@@ -25,6 +25,7 @@
#include <drm/drmP.h>
#include "radeon.h"
#include "radeon_asic.h"
+#include "radeon_trace.h"
#include "cikd.h"
/* sdma */
@@ -657,6 +658,8 @@ void cik_sdma_vm_set_page(struct radeon_device *rdev,
uint64_t value;
unsigned ndw;
+ trace_radeon_vm_set_page(pe, addr, count, incr, r600_flags);
+
if (flags & RADEON_VM_PAGE_SYSTEM) {
while (count) {
ndw = count * 2;
@@ -24,6 +24,7 @@
#include <drm/drmP.h>
#include "radeon.h"
#include "radeon_asic.h"
+#include "radeon_trace.h"
#include "nid.h"
u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev);
@@ -260,6 +261,8 @@ void cayman_dma_vm_set_page(struct radeon_device *rdev,
uint64_t value;
unsigned ndw;
+ trace_radeon_vm_set_page(pe, addr, count, incr, r600_flags);
+
if ((flags & RADEON_VM_PAGE_SYSTEM) || (count == 1)) {
while (count) {
ndw = count * 2;
@@ -47,6 +47,30 @@ TRACE_EVENT(radeon_cs,
__entry->fences)
);
+TRACE_EVENT(radeon_vm_set_page,
+ TP_PROTO(uint64_t pe, uint64_t addr, unsigned count,
+ uint32_t incr, uint32_t flags),
+ TP_ARGS(pe, addr, count, incr, flags),
+ TP_STRUCT__entry(
+ __field(u64, pe)
+ __field(u64, addr)
+ __field(u32, count)
+ __field(u32, incr)
+ __field(u32, flags)
+ ),
+
+ TP_fast_assign(
+ __entry->pe = pe;
+ __entry->addr = addr;
+ __entry->count = count;
+ __entry->incr = incr;
+ __entry->flags = flags;
+ ),
+ TP_printk("pe=%010Lx, addr=%010Lx, incr=%u, flags=%08x, count=%u",
+ __entry->pe, __entry->addr, __entry->incr,
+ __entry->flags, __entry->count)
+);
+
DECLARE_EVENT_CLASS(radeon_fence_request,
TP_PROTO(struct drm_device *dev, u32 seqno),
@@ -24,6 +24,7 @@
#include <drm/drmP.h>
#include "radeon.h"
#include "radeon_asic.h"
+#include "radeon_trace.h"
#include "sid.h"
u32 si_gpu_check_soft_reset(struct radeon_device *rdev);
@@ -79,6 +80,8 @@ void si_dma_vm_set_page(struct radeon_device *rdev,
uint64_t value;
unsigned ndw;
+ trace_radeon_vm_set_page(pe, addr, count, incr, r600_flags);
+
if (flags & RADEON_VM_PAGE_SYSTEM) {
while (count) {
ndw = count * 2;