From patchwork Fri Nov 15 13:01:51 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 3188151 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 17A789F39E for ; Fri, 15 Nov 2013 13:00:19 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7CECF207E7 for ; Fri, 15 Nov 2013 13:00:14 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id D8E43207EF for ; Fri, 15 Nov 2013 13:00:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6EF55FB8A2; Fri, 15 Nov 2013 05:00:05 -0800 (PST) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id C0E66FB89F; Fri, 15 Nov 2013 05:00:01 -0800 (PST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP; 15 Nov 2013 05:00:01 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.93,535,1378882800"; d="scan'208";a="435802005" Received: from jnikula-mobl1.fi.intel.com (HELO localhost) ([10.237.72.185]) by orsmga002.jf.intel.com with ESMTP; 15 Nov 2013 04:59:59 -0800 From: Jani Nikula To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Subject: [PATCH 2/2] drm/i915/dp: check eDP display control capability registers Date: Fri, 15 Nov 2013 15:01:51 +0200 Message-Id: <1384520511-24267-2-git-send-email-jani.nikula@intel.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1384520511-24267-1-git-send-email-jani.nikula@intel.com> References: <1384520511-24267-1-git-send-email-jani.nikula@intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Cc: jani.nikula@intel.com X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: dri-devel-bounces@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Debug print the capabilities, and flag an error if the panel does not support adjusting backlight through the BL_PWM_DIM pin, requiring backlight control through DPCD. I haven't seen such panels yet, but it's a matter of time. Give ourselves a reminder when we need to fix this for real. Signed-off-by: Jani Nikula Reviewed-by: Thierry Reding --- drivers/gpu/drm/i915/intel_dp.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index cbf33be..ea4f3d1 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -2816,6 +2816,20 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) dev_priv->psr.sink_support = true; DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); } + + if (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & + DP_DPCD_DISPLAY_CONTROL_CAP) { + u8 ctrl[4] = { 0 }; + + intel_dp_aux_native_read(intel_dp, DP_EDP_REV, + ctrl, sizeof(ctrl)); + DRM_DEBUG_KMS("eDP DPCD CTRL %02x %02x %02x %02x\n", + ctrl[0], ctrl[1], ctrl[2], ctrl[3]); + + /* We don't support DPCD backlight control yet. */ + if (ctrl[0] && (ctrl[1] & 1) && !(ctrl[2] & 1)) + DRM_ERROR("eDP AUX backlight control only\n"); + } } if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &