From patchwork Mon Nov 18 08:38:36 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shirish S X-Patchwork-Id: 3199431 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 221CD9F3A0 for ; Tue, 19 Nov 2013 01:19:56 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DB35820320 for ; Tue, 19 Nov 2013 01:19:54 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id E336F2030E for ; Tue, 19 Nov 2013 01:19:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1C27AFC036; Mon, 18 Nov 2013 17:19:42 -0800 (PST) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mailout1.samsung.com (mailout1.samsung.com [203.254.224.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 2B398105B76 for ; Mon, 18 Nov 2013 00:19:05 -0800 (PST) Received: from epcpsbgr1.samsung.com (u141.gpu120.samsung.co.kr [203.254.230.141]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MWG003NY9RG54X0@mailout1.samsung.com> for dri-devel@lists.freedesktop.org; Mon, 18 Nov 2013 17:18:57 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.125]) by epcpsbgr1.samsung.com (EPCPMTA) with SMTP id 81.80.10672.17DC9825; Mon, 18 Nov 2013 17:18:57 +0900 (KST) X-AuditID: cbfee68d-b7fa16d0000029b0-e6-5289cd7129c9 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id D8.58.09687.17DC9825; Mon, 18 Nov 2013 17:18:57 +0900 (KST) Received: from chromeserver-PowerEdge-T410.sisodomain.com ([107.108.73.106]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MWG002UA9RAMR70@mmp2.samsung.com>; Mon, 18 Nov 2013 17:18:56 +0900 (KST) From: Shirish S To: dri-devel@lists.freedesktop.org, inki.dae@samsung.com, devicetree@vger.kernel.org, mark.rutland@arm.com Subject: [PATCH 4/4] drm: exynos: hdmi: Add dt support for hdmiphy settings Date: Mon, 18 Nov 2013 14:08:36 +0530 Message-id: <1384763916-31868-5-git-send-email-s.shirish@samsung.com> X-Mailer: git-send-email 1.7.10.4 In-reply-to: <1384763916-31868-1-git-send-email-s.shirish@samsung.com> References: <1384763916-31868-1-git-send-email-s.shirish@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrFLMWRmVeSWpSXmKPExsWyRsSkVrfwbGeQwewPAhbzj5xjtbjy9T2b xaT7E1gsll6/yGQxbfZGRou7G84yWjTtOMhmMWPySzYHDo8189YwesxuuMjicb/7OJNH35ZV jB6fN8kFsEZx2aSk5mSWpRbp2yVwZdx9PZOxYLdBxa0l/9kbGE+pdTFyckgImEgcPX+CFcIW k7hwbz1bFyMXh5DAUkaJb9d2sMAUNU5dywhiCwlMZ5TYtVQPomg2k8TL341MIAk2AXWJi5NX M4PYIgK5EodnfQKzmQVyJLbOuwu2QVjAW2Le3tlAgzg4WARUJT5OsQUJ8wq4Skycf5oRYpei RPezCWwgNqeAm8T1exOYIfa6Slw7dIYZZK+EwDJ2iZ2H3oElWAQEJL5NPsQCMlNCQFZi0wFm iDmSEgdX3GCZwCi8gJFhFaNoakFyQXFSepGhXnFibnFpXrpecn7uJkZguJ/+96x3B+PtA9aH GJOBxk1klhJNzgfGS15JvKGxmZGFqYmpsZG5pRlpwkrivEkPk4KEBNITS1KzU1MLUovii0pz UosPMTJxcEo1MCrab44RXpNktViZI/Xdlge3FbbccjcTc0tzK0mc9Nfn15vPz2+vT+bKnujn 3dsUztZRz+4ufv3giSjv+OYXs2t6Si8vC+OLsJ5ftJrTaIKrm8H0NfP/L4/89v9D/POIYrGI TmYtvosFn6SYZOZtqj+235mN6eHyh5e27lVm5QnR2l2nfbfJQ4mlOCPRUIu5qDgRABAywXmN AgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrOIsWRmVeSWpSXmKPExsVy+t9jQd3Cs51BBh/3sVvMP3KO1eLK1/ds FpPuT2CxWHr9IpPFtNkbGS3ubjjLaNG04yCbxYzJL9kcODzWzFvD6DG74SKLx/3u40wefVtW MXp83iQXwBrVwGiTkZqYklqkkJqXnJ+SmZduq+QdHO8cb2pmYKhraGlhrqSQl5ibaqvk4hOg 65aZA3SMkkJZYk4pUCggsbhYSd8O04TQEDddC5jGCF3fkCC4HiMDNJCwhjHj7uuZjAW7DSpu LfnP3sB4Sq2LkZNDQsBEonHqWkYIW0ziwr31bCC2kMB0RoldS/W6GLmA7NlMEi9/NzKBJNgE 1CUuTl7NDGKLCORKHJ71CcxmFsiR2DrvLiuILSzgLTFv72ygoRwcLAKqEh+n2IKEeQVcJSbO Pw21S1Gi+9kEsF2cAm4S1+9NYIbY6ypx7dAZ5gmMvAsYGVYxiqYWJBcUJ6XnGuoVJ+YWl+al 6yXn525iBEfTM6kdjCsbLA4xCnAwKvHwaoR1BgmxJpYVV+YeYpTgYFYS4f1zHCjEm5JYWZVa lB9fVJqTWnyIMRnoqInMUqLJ+cBIzyuJNzQ2MTc1NrU0sTAxsyRNWEmc90CrdaCQQHpiSWp2 ampBahHMFiYOTqkGxnWze4XfcCryxQWo9DAX7BTfqtTfq911+owPQ8Lv8xVqbun7hKyFuTZP S7qrdvd1+4m/14tvftPf3Sha9efgUo6fm56Vr4s5s/jT9xUcM4ruRC7s789etv3basanZQf2 7NWuv1OS8O7tnZvS649W3lhvfOnZHQa+THPrVjvFvAWT597S/HHVPl+JpTgj0VCLuag4EQDH oT/h6gIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-Mailman-Approved-At: Mon, 18 Nov 2013 17:19:36 -0800 Cc: sw0312.kim@samsung.com, shirish@chromium.org, Shirish S X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: dri-devel-bounces@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds dt support to hdmiphy config settings as it is board specific and depends on the signal pattern of board. Signed-off-by: Shirish S --- .../devicetree/bindings/video/exynos_hdmi.txt | 33 +++++++++ drivers/gpu/drm/exynos/exynos_hdmi.c | 77 +++++++++++++++++++- 2 files changed, 106 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt b/Documentation/devicetree/bindings/video/exynos_hdmi.txt index 323983b..1021c74 100644 --- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt +++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt @@ -13,6 +13,31 @@ Required properties: b) pin number within the gpio controller. c) optional flags and pull up/down. +- hdmiphy-configs: following information about the hdmiphy config settings. + a) "nr-configs" specifies the number of pixel clocks supported. + b) "config: config" specifies the phy configuration settings, + where 'N' denotes the number of configuration, since every + pixel clock can have its unique configuration. + "pixel-clock" specifies the pixel clock + "conifig-de-emphasis-level" provides fine control of TMDS data + pre emphasis, below shown is example for + data de-emphasis register at address 0x145D0040. + hdmiphy@38[16] for bits[3:0] permitted values are in + the range of 760 mVdiff to 1400 mVdiff at 20mVdiff + increments for every LSB + hdmiphy@38[16] for bits[7:4] permitted values are in + the range of 0dB to -7.45dB at increments of -0.45dB + for every LSB. + "config-clock-level" provides fine control of TMDS data + amplitude for each channel, + for example if 0x145D005C is the address of clock level + register then, + hdmiphy@38[23] for bits [1:0] permitted values are in + the range of 0 mVdiff & 60 mVdiff for each channel at + increments 20 mVdiff of amplitude levels for every LSB, + hdmiphy@38[23] for bits [7:3] permitted values are in + the range of 790 and 1430 mV at 20mV increments for + every LSB. Example: hdmi { @@ -20,4 +45,12 @@ Example: reg = <0x14530000 0x100000>; interrupts = <0 95 0>; hpd-gpio = <&gpx3 7 1>; + hdmiphy-configs { + nr-configs = <1>; + config0: config0 { + pixel-clock = <25200000>; + config-de-emphasis-level = /bits/ 8 <0x26>; + config-clock-level = /bits/ 8 < 0x66>; + }; + } }; diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c index 32ce9a6..5f599e3 100644 --- a/drivers/gpu/drm/exynos/exynos_hdmi.c +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c @@ -197,6 +197,9 @@ struct hdmi_context { struct hdmi_resources res; + struct hdmiphy_config *confs; + int nr_confs; + int hpd_gpio; enum hdmi_type type; @@ -256,7 +259,7 @@ static const struct hdmiphy_config hdmiphy_v13_configs[] = { }, }; -static const struct hdmiphy_config hdmiphy_v14_configs[] = { +static struct hdmiphy_config hdmiphy_v14_configs[] = { { .pixel_clock = 25200000, .conf = { @@ -785,8 +788,8 @@ static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock) confs = hdmiphy_v13_configs; count = ARRAY_SIZE(hdmiphy_v13_configs); } else if (hdata->type == HDMI_TYPE14) { - confs = hdmiphy_v14_configs; - count = ARRAY_SIZE(hdmiphy_v14_configs); + confs = hdata->confs; + count = hdata->nr_confs; } else return -EINVAL; @@ -1415,7 +1418,7 @@ static void hdmiphy_conf_apply(struct hdmi_context *hdata) if (hdata->type == HDMI_TYPE13) hdmiphy_data = hdmiphy_v13_configs[i].conf; else - hdmiphy_data = hdmiphy_v14_configs[i].conf; + hdmiphy_data = hdata->confs[i].conf; memcpy(buffer, hdmiphy_data, 32); ret = i2c_master_send(hdata->hdmiphy_port, buffer, 32); @@ -1894,6 +1897,63 @@ fail: return -ENODEV; } +static int drm_hdmi_dt_parse_phy_conf(struct platform_device *pdev, + struct hdmi_context *hdata) +{ + struct device *dev = &pdev->dev; + struct device_node *dev_np = dev->of_node; + struct device_node *phy_conf, *cfg_np; + int i, pixel_clock = 0; + + /* Initialize with default config */ + hdata->confs = hdmiphy_v14_configs; + hdata->nr_confs = ARRAY_SIZE(hdmiphy_v14_configs); + + phy_conf = of_find_node_by_name(dev_np, "hdmiphy-configs"); + if (phy_conf == NULL) { + hdata->nr_confs = ARRAY_SIZE(hdmiphy_v14_configs); + DRM_ERROR("Did not find hdmiphy-configs node\n"); + return -ENODEV; + } + + for_each_child_of_node(phy_conf, cfg_np) { + if (!of_find_property(cfg_np, "pixel-clock", NULL)) + continue; + + if (of_property_read_u32(cfg_np, "pixel-clock", + &pixel_clock, 1)) { + DRM_ERROR("Failed to get pixel clock\n"); + return -EINVAL; + } + + for (i = 0; i < ARRAY_SIZE(hdmiphy_v14_configs); i++) { + if (hdata->confs[i].pixel_clock == pixel_clock) + /* Update the data de-emphasis and data level */ + if (of_property_read_u8_array(cfg_np, + "config-de-emphasis-level", + &hdata->confs[i].conf[16], 1)) { + DRM_ERROR("Failed to get conf\n"); + return -EINVAL; + } + if (of_property_read_u8_array(cfg_np, + "config-de-emphasis-level", + &hdata->confs[i].conf[16], 1)) { + DRM_ERROR("Failed to get conf\n"); + return -EINVAL; + } + /* Update the clock level diff */ + if (of_property_read_u8_array(cfg_np, + "config-clock-level", + &hdata->confs[i].conf[23], 1)) { + DRM_ERROR("Failed to get conf\n"); + return -EINVAL; + } + } + } + return 0; + +} + static struct s5p_hdmi_platform_data *drm_hdmi_dt_parse_pdata (struct device *dev) { @@ -2024,6 +2084,15 @@ static int hdmi_probe(struct platform_device *pdev) goto err_hdmiphy; } + /* get hdmiphy confs */ + if (hdata->type == HDMI_TYPE14) { + ret = drm_hdmi_dt_parse_phy_conf(pdev, hdata); + if (ret) { + DRM_ERROR("failed to get user defined config,will use + default configs, eye diagram tests may fail\n"); + } + } + hdmi_display.dev = dev; exynos_drm_display_register(&hdmi_display);