From patchwork Fri Jan 10 02:19:12 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilia Mirkin X-Patchwork-Id: 3464041 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 93B89C02DC for ; Fri, 10 Jan 2014 02:19:56 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B24EF2011B for ; Fri, 10 Jan 2014 02:19:55 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id D08B72010F for ; Fri, 10 Jan 2014 02:19:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2FEA5106A9C; Thu, 9 Jan 2014 18:19:47 -0800 (PST) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-qc0-f175.google.com (mail-qc0-f175.google.com [209.85.216.175]) by gabe.freedesktop.org (Postfix) with ESMTP id 10273106A9A; Thu, 9 Jan 2014 18:19:43 -0800 (PST) Received: by mail-qc0-f175.google.com with SMTP id x13so2375988qcv.34 for ; Thu, 09 Jan 2014 18:19:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=oUqVjluK/XZdMwIOr6GIvPq4GBZTPaq4dc8CraEiR/g=; b=xj2z2RJ16g3eQZvmCpK+QgVVF52L2kiXW5kU9CbTFg1IkRk/hQNSeedqmO/bFILp12 MZ4oqJ0H/Iwz5FFxJ25Gs0hrlTNrf9TydHHfoxFvtZgPqvEK0BHxNyfhnHXmTFLI+3Zs 9TFatD5S1eu0EoXKKtFe13U8EhYV1TlI5abW1UjdKRCh41Emczp1p8Pi16ksocdY0fC9 rDwvByZTMwEiKq/JCYp7dlXEIS/e4UTizc1ayTucbGth9X0TRlh+dbqvntpMeq8h5ZGd jXIZ2Mt5zMtwxTbvkPvd/0FD1Y5B+05bLHoUqearfULzkDi7zZBmVjy8SyTPFXYgcRCh XB6g== X-Received: by 10.224.103.131 with SMTP id k3mr1970305qao.102.1389320383575; Thu, 09 Jan 2014 18:19:43 -0800 (PST) Received: from localhost.localdomain (cpe-74-71-29-187.nyc.res.rr.com. [74.71.29.187]) by mx.google.com with ESMTPSA id f5sm9469922qas.11.2014.01.09.18.19.39 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 Jan 2014 18:19:41 -0800 (PST) From: Ilia Mirkin To: Ben Skeggs Subject: [PATCH 2/3] drm/nv50/devinit: set the disable mask based on the hwunits registers Date: Thu, 9 Jan 2014 21:19:12 -0500 Message-Id: <1389320353-21375-2-git-send-email-imirkin@alum.mit.edu> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1389320353-21375-1-git-send-email-imirkin@alum.mit.edu> References: <1389320353-21375-1-git-send-email-imirkin@alum.mit.edu> Cc: nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: dri-devel-bounces@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This will turn off PDISPLAY/PCRYPT/PCOPY0/video engines on cards where they are marked as disabled either by the hardware of VBIOS. See https://bugs.freedesktop.org/show_bug.cgi?id=58378 Signed-off-by: Ilia Mirkin --- An earlier version of this patch was tested. I added the DISP disable since then, and rejiggered the way the function was called (turns out that nv50_init function is called by nvc0 as well). drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.c | 72 ++++++++++++++++++++++ drivers/gpu/drm/nouveau/core/subdev/devinit/priv.h | 2 + 2 files changed, 74 insertions(+) diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.c index 6df7224..f4d32c6 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.c +++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.c @@ -74,6 +74,74 @@ nv50_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq) return 0; } +static void +nv50_disable_engines(struct nouveau_object *object) +{ + struct nouveau_device *device = nv_device(object); + bool vdec; + u32 r154c; + + /* check for disabled engines */ + vdec = nv_rd32(device, 0x1540) & 0x40000000; + if (device->chipset > 0x50) + r154c = nv_rd32(device, 0x154c); + else + r154c = ~0U; + + if (!(r154c & 0x4)) + device->disable_mask |= 1ULL << NVDEV_ENGINE_DISP; + + switch (device->chipset) { + case 0x50: + if (!vdec) + device->disable_mask |= 1ULL << NVDEV_ENGINE_MPEG; + break; + case 0x84: + case 0x86: + case 0x92: + case 0x94: + case 0x96: + case 0xa0: + if (!vdec) { + device->disable_mask |= 1ULL << NVDEV_ENGINE_MPEG; + device->disable_mask |= 1ULL << NVDEV_ENGINE_VP; + } + if (!vdec || !(r154c & 0x20)) + device->disable_mask |= 1ULL << NVDEV_ENGINE_BSP; + if (!vdec || !(r154c & 0x40)) + device->disable_mask |= 1ULL << NVDEV_ENGINE_CRYPT; + break; + case 0x98: + case 0xaa: + case 0xac: + if (!vdec) { + device->disable_mask |= 1ULL << NVDEV_ENGINE_VP; + device->disable_mask |= 1ULL << NVDEV_ENGINE_PPP; + } + if (!vdec || !(r154c & 0x20)) + device->disable_mask |= 1ULL << NVDEV_ENGINE_BSP; + if (!(r154c & 0x40)) + device->disable_mask |= 1ULL << NVDEV_ENGINE_CRYPT; + break; + case 0xaf: + if (!(r154c & 0x40)) + device->disable_mask |= 1ULL << NVDEV_ENGINE_VIC; + /* fallthrough */ + case 0xa3: + case 0xa5: + case 0xa8: + if (!vdec) { + device->disable_mask |= 1ULL << NVDEV_ENGINE_VP; + device->disable_mask |= 1ULL << NVDEV_ENGINE_PPP; + } + if (!(r154c & 0x20)) + device->disable_mask |= 1ULL << NVDEV_ENGINE_BSP; + if (!(r154c & 0x200)) + device->disable_mask |= 1ULL << NVDEV_ENGINE_COPY0; + break; + } +} + int nv50_devinit_init(struct nouveau_object *object) { @@ -117,6 +185,9 @@ nv50_devinit_init(struct nouveau_object *object) i++; } + if (priv->disable_engines) + priv->disable_engines(object); + return 0; } @@ -134,6 +205,7 @@ nv50_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return ret; priv->base.pll_set = nv50_devinit_pll_set; + priv->disable_engines = nv50_disable_engines; return 0; } diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/priv.h b/drivers/gpu/drm/nouveau/core/subdev/devinit/priv.h index 7d622e2..f17a368 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/devinit/priv.h +++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/priv.h @@ -18,6 +18,8 @@ void setPLL_double_lowregs(struct nouveau_devinit *, u32, struct nouveau_pll_val struct nv50_devinit_priv { struct nouveau_devinit base; + + void (*disable_engines)(struct nouveau_object *); }; int nv50_devinit_init(struct nouveau_object *);