| Message ID | 1391224618-3794-11-git-send-email-acourbot@nvidia.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Sat, Feb 1, 2014 at 1:16 PM, Alexandre Courbot <acourbot@nvidia.com> wrote: > GK20A's timer is directly attached to the system timer and cannot be > calibrated. Skip the calibration phase on that chip since the > corresponding registers do not exist. Just a curiosity: What timer resolution does the HW initialise at? > > Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> > --- > drivers/gpu/drm/nouveau/core/subdev/timer/nv04.c | 19 +++++++++++++------ > 1 file changed, 13 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/nouveau/core/subdev/timer/nv04.c b/drivers/gpu/drm/nouveau/core/subdev/timer/nv04.c > index c0bdd10..822fe0d 100644 > --- a/drivers/gpu/drm/nouveau/core/subdev/timer/nv04.c > +++ b/drivers/gpu/drm/nouveau/core/subdev/timer/nv04.c > @@ -185,6 +185,10 @@ nv04_timer_init(struct nouveau_object *object) > if (ret) > return ret; > > + /* gk20a does not have the calibration registers */ > + if (device->chipset == 0xea) > + goto skip_clk_init; > + > /* aim for 31.25MHz, which gives us nanosecond timestamps */ > d = 1000000 / 32; > > @@ -235,20 +239,23 @@ nv04_timer_init(struct nouveau_object *object) > d >>= 1; > } > > - /* restore the time before suspend */ > - lo = priv->suspend_time; > - hi = (priv->suspend_time >> 32); > - > nv_debug(priv, "input frequency : %dHz\n", f); > nv_debug(priv, "input multiplier: %d\n", m); > nv_debug(priv, "numerator : 0x%08x\n", n); > nv_debug(priv, "denominator : 0x%08x\n", d); > nv_debug(priv, "timer frequency : %dHz\n", (f * m) * d / n); > - nv_debug(priv, "time low : 0x%08x\n", lo); > - nv_debug(priv, "time high : 0x%08x\n", hi); > > nv_wr32(priv, NV04_PTIMER_NUMERATOR, n); > nv_wr32(priv, NV04_PTIMER_DENOMINATOR, d); > + > +skip_clk_init: > + /* restore the time before suspend */ > + lo = priv->suspend_time; > + hi = (priv->suspend_time >> 32); > + > + nv_debug(priv, "time low : 0x%08x\n", lo); > + nv_debug(priv, "time high : 0x%08x\n", hi); > + > nv_wr32(priv, NV04_PTIMER_INTR_0, 0xffffffff); > nv_wr32(priv, NV04_PTIMER_INTR_EN_0, 0x00000000); > nv_wr32(priv, NV04_PTIMER_TIME_1, hi); > -- > 1.8.5.3 > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/dri-devel
On 02/04/2014 12:55 PM, Ben Skeggs wrote: > On Sat, Feb 1, 2014 at 1:16 PM, Alexandre Courbot <acourbot@nvidia.com> wrote: >> GK20A's timer is directly attached to the system timer and cannot be >> calibrated. Skip the calibration phase on that chip since the >> corresponding registers do not exist. > Just a curiosity: What timer resolution does the HW initialise at? On T124 the timer input is the oscillator clock, which depending on the device can run between 12 and 48Mhz (IIUC).
On 02/04/2014 01:39 AM, Alexandre Courbot wrote: > On 02/04/2014 12:55 PM, Ben Skeggs wrote: >> On Sat, Feb 1, 2014 at 1:16 PM, Alexandre Courbot >> <acourbot@nvidia.com> wrote: >>> GK20A's timer is directly attached to the system timer and cannot be >>> calibrated. Skip the calibration phase on that chip since the >>> corresponding registers do not exist. >> Just a curiosity: What timer resolution does the HW initialise at? > > On T124 the timer input is the oscillator clock, which depending on the > device can run between 12 and 48Mhz (IIUC). On the one Tegra124 board we support upstream, the crystal is 12MHz. I believe this is a typical/common value; almost all the Tegra boards we support upstream run at this rate.
diff --git a/drivers/gpu/drm/nouveau/core/subdev/timer/nv04.c b/drivers/gpu/drm/nouveau/core/subdev/timer/nv04.c index c0bdd10..822fe0d 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/timer/nv04.c +++ b/drivers/gpu/drm/nouveau/core/subdev/timer/nv04.c @@ -185,6 +185,10 @@ nv04_timer_init(struct nouveau_object *object) if (ret) return ret; + /* gk20a does not have the calibration registers */ + if (device->chipset == 0xea) + goto skip_clk_init; + /* aim for 31.25MHz, which gives us nanosecond timestamps */ d = 1000000 / 32; @@ -235,20 +239,23 @@ nv04_timer_init(struct nouveau_object *object) d >>= 1; } - /* restore the time before suspend */ - lo = priv->suspend_time; - hi = (priv->suspend_time >> 32); - nv_debug(priv, "input frequency : %dHz\n", f); nv_debug(priv, "input multiplier: %d\n", m); nv_debug(priv, "numerator : 0x%08x\n", n); nv_debug(priv, "denominator : 0x%08x\n", d); nv_debug(priv, "timer frequency : %dHz\n", (f * m) * d / n); - nv_debug(priv, "time low : 0x%08x\n", lo); - nv_debug(priv, "time high : 0x%08x\n", hi); nv_wr32(priv, NV04_PTIMER_NUMERATOR, n); nv_wr32(priv, NV04_PTIMER_DENOMINATOR, d); + +skip_clk_init: + /* restore the time before suspend */ + lo = priv->suspend_time; + hi = (priv->suspend_time >> 32); + + nv_debug(priv, "time low : 0x%08x\n", lo); + nv_debug(priv, "time high : 0x%08x\n", hi); + nv_wr32(priv, NV04_PTIMER_INTR_0, 0xffffffff); nv_wr32(priv, NV04_PTIMER_INTR_EN_0, 0x00000000); nv_wr32(priv, NV04_PTIMER_TIME_1, hi);
GK20A's timer is directly attached to the system timer and cannot be calibrated. Skip the calibration phase on that chip since the corresponding registers do not exist. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> --- drivers/gpu/drm/nouveau/core/subdev/timer/nv04.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-)