From patchwork Thu Feb 27 08:11:39 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Carl Worth X-Patchwork-Id: 3737581 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 242F19F382 for ; Fri, 28 Feb 2014 02:24:41 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 28B442021F for ; Fri, 28 Feb 2014 02:24:40 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 690CB20225 for ; Fri, 28 Feb 2014 02:24:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AE47AFBA93; Thu, 27 Feb 2014 18:24:20 -0800 (PST) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from arlo.cworth.org (arlo.cworth.org [50.126.95.6]) by gabe.freedesktop.org (Postfix) with ESMTP id A02D3FAE87; Thu, 27 Feb 2014 00:11:46 -0800 (PST) Received: from localhost (localhost [127.0.0.1]) by arlo.cworth.org (Postfix) with ESMTP id E743F6DE14C8; Thu, 27 Feb 2014 00:11:43 -0800 (PST) X-Virus-Scanned: Debian amavisd-new at arlo.cworth.org Received: from arlo.cworth.org ([127.0.0.1]) by localhost (arlo.cworth.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 7NK1srIf-00V; Thu, 27 Feb 2014 00:11:39 -0800 (PST) Received: from yoom.home.cworth.org (localhost [IPv6:::1]) by arlo.cworth.org (Postfix) with ESMTP id 3D9426DE14AA; Thu, 27 Feb 2014 00:11:39 -0800 (PST) From: Carl Worth To: intel-gfx@lists.freedesktop.org Subject: [PATCH] drm/i915/dp: Allow for 5.4Gbps for Haswell. Date: Thu, 27 Feb 2014 00:11:39 -0800 Message-Id: <1393488699-6265-1-git-send-email-cworth@cworth.org> X-Mailer: git-send-email 1.9.0 X-Mailman-Approved-At: Thu, 27 Feb 2014 18:24:12 -0800 Cc: Daniel Vetter , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Carl Worth X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: dri-devel-bounces@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP With Haswell, 5.4Gbps is supported. And almost all of the code was already in place already. All that was missing was this tiny bit of additional wiring. Signed-off-by: Carl Worth Reviewed-by: Keith Packard --- drivers/gpu/drm/i915/intel_dp.c | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 57552eb..ce9739e 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -101,7 +101,11 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp) case DP_LINK_BW_1_62: case DP_LINK_BW_2_7: break; - case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */ + case DP_LINK_BW_5_4: + /* XXX: But not HASWELL ULX. */ + if (IS_HASWELL(intel_dp_to_dev(intel_dp))) + break; + /* Prior to HASWELL, maximum support is for 2.7 Gbps */ max_link_bw = DP_LINK_BW_2_7; break; default: @@ -810,12 +814,24 @@ intel_dp_compute_config(struct intel_encoder *encoder, enum port port = dp_to_dig_port(intel_dp)->port; struct intel_crtc *intel_crtc = encoder->new_crtc; struct intel_connector *intel_connector = intel_dp->attached_connector; - int lane_count, clock; + int lane_count; int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); - int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; int bpp, mode_rate; - static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; int link_avail, link_clock; + int max_link_bw; + /* The clock and max_clock values are an index into bws. */ + int clock, max_clock = 0; + static int bws[3] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4}; + + max_link_bw = intel_dp_max_link_bw(intel_dp); + + for (clock = 0; clock < ARRAY_SIZE(bws); clock++) { + if (bws[clock] == max_link_bw) { + max_clock = clock; + break; + } + } + if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) pipe_config->has_pch_encoder = true;