| Message ID | 1396967856-27470-3-git-send-email-t.stanislaws@samsung.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi Tomasz, On 04/08/2014 04:37 PM, Tomasz Stanislawski wrote: > The HDMIPHY (physical interface) is controlled by a single > bit in a power controller's regiter. It was implemented > as clock. It was a simple but effective hack. This power controller register has also bits to control HDMI clock divider ratio. I guess current drivers do not change it, but how do you want to implement access to it if some HDMI driver in the future will need to change ratio. I guess in case of clk it would be easier. Regards Andrzej
Hi Andrzej, On 9 April 2014 16:00, Andrzej Hajda <a.hajda@samsung.com> wrote: > Hi Tomasz, > > On 04/08/2014 04:37 PM, Tomasz Stanislawski wrote: >> The HDMIPHY (physical interface) is controlled by a single >> bit in a power controller's regiter. It was implemented >> as clock. It was a simple but effective hack. > > This power controller register has also bits to control HDMI clock > divider ratio. I guess current drivers do not change it, but how do you > want to implement access to it if some HDMI driver in the future will > need to change ratio. I guess in case of clk it would be easier. If it is really required to change this divider, it should be registered as a clock provider in clock driver exposing single divider clock. Regards, Rahul Sharma > > Regards > Andrzej > > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/dri-devel
Hi Andrzej, This issue could be solved by exporting a regmap from PMU driver or Exynos clock provider for the usage by exynos-simple-phy. The operations on PHYs from exynos-simple-phy provider would be chained to PMU driver and protected by a spinlock in the regmap. Luckily, the divider is not used as far as I know. Regards, Tomasz Stanislawski On 04/09/2014 12:30 PM, Andrzej Hajda wrote: > Hi Tomasz, > > On 04/08/2014 04:37 PM, Tomasz Stanislawski wrote: >> The HDMIPHY (physical interface) is controlled by a single >> bit in a power controller's regiter. It was implemented >> as clock. It was a simple but effective hack. > > This power controller register has also bits to control HDMI clock > divider ratio. I guess current drivers do not change it, but how do you > want to implement access to it if some HDMI driver in the future will > need to change ratio. I guess in case of clk it would be easier. > > Regards > Andrzej > >
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c index 9a6d652..ef1cdd0 100644 --- a/drivers/gpu/drm/exynos/exynos_hdmi.c +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c @@ -36,6 +36,7 @@ #include <linux/i2c.h> #include <linux/of_gpio.h> #include <linux/hdmi.h> +#include <linux/phy/phy.h> #include <drm/exynos_drm.h> @@ -74,8 +75,8 @@ struct hdmi_resources { struct clk *sclk_hdmi; struct clk *sclk_pixel; struct clk *sclk_hdmiphy; - struct clk *hdmiphy; struct clk *mout_hdmi; + struct phy *hdmiphy; struct regulator_bulk_data *regul_bulk; int regul_count; }; @@ -1854,7 +1855,7 @@ static void hdmi_poweron(struct exynos_drm_display *display) if (regulator_bulk_enable(res->regul_count, res->regul_bulk)) DRM_DEBUG_KMS("failed to enable regulator bulk\n"); - clk_prepare_enable(res->hdmiphy); + phy_power_on(res->hdmiphy); clk_prepare_enable(res->hdmi); clk_prepare_enable(res->sclk_hdmi); @@ -1881,7 +1882,7 @@ static void hdmi_poweroff(struct exynos_drm_display *display) clk_disable_unprepare(res->sclk_hdmi); clk_disable_unprepare(res->hdmi); - clk_disable_unprepare(res->hdmiphy); + phy_power_off(res->hdmiphy); regulator_bulk_disable(res->regul_count, res->regul_bulk); pm_runtime_put_sync(hdata->dev); @@ -1977,9 +1978,9 @@ static int hdmi_resources_init(struct hdmi_context *hdata) DRM_ERROR("failed to get clock 'sclk_hdmiphy'\n"); goto fail; } - res->hdmiphy = devm_clk_get(dev, "hdmiphy"); + res->hdmiphy = devm_phy_get(dev, "hdmiphy"); if (IS_ERR(res->hdmiphy)) { - DRM_ERROR("failed to get clock 'hdmiphy'\n"); + DRM_ERROR("failed to get phy 'hdmiphy'\n"); goto fail; } res->mout_hdmi = devm_clk_get(dev, "mout_hdmi");
The HDMIPHY (physical interface) is controlled by a single bit in a power controller's regiter. It was implemented as clock. It was a simple but effective hack. This patch makes HDMI driver to control HDMIPHY via PHY interface. Signed-off-by: Tomasz Stanislawski <t.stanislaws@samsung.com> --- drivers/gpu/drm/exynos/exynos_hdmi.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-)