| Message ID | 1397735629-24028-1-git-send-email-yj44.cho@samsung.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi again, On 04/17/2014 01:53 PM, YoungJun Cho wrote: > In case of using CPU interface panel, the relevant registers should be set. > So this patch adds relevant dt bindings. > > Changelog v2: > - Changes "samsung,sysreg-phandle" to "samsung,sysreg" > > Signed-off-by: YoungJun Cho <yj44.cho@samsung.com> > Signed-off-by: Inki Dae <inki.dae@samsung.com> > Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> > --- > .../devicetree/bindings/video/samsung-fimd.txt | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/Documentation/devicetree/bindings/video/samsung-fimd.txt b/Documentation/devicetree/bindings/video/samsung-fimd.txt > index 2dad41b..6ea1adc 100644 > --- a/Documentation/devicetree/bindings/video/samsung-fimd.txt > +++ b/Documentation/devicetree/bindings/video/samsung-fimd.txt > @@ -44,6 +44,15 @@ Optional Properties: > - display-timings: timing settings for FIMD, as described in document [1]. > Can be used in case timings cannot be provided otherwise > or to override timings provided by the panel. > +- samsung,sysreg: handle to syscon used to control the system registers > +- vidout-i80-ldi: boolean to support i80 interface instead of rgb one > +- cs-setup: clock cycles for the active period of address signal enable until > + chip select is enable in i80 interface > +- wr-setup: clock cycles for the active period of CS signal enable until > + write signal is enable in i80 interface > +- wr-act: clock cycles for the active period of CS enable in i80 interface > +- wr-hold: clock cycles for the active period of CS disable until write signal > + is disable in i80 interface As Laurent wrote earlier it would be good to consider providing these properties by panel. Panel can pass it to DSI probably via mipi_dsi_device structure. DSI to FIMD can use exynos drm_framework probably. Anyway if you add optional properties please add info about default value, ie when property is not present. Regards Andrzej > > The device node can contain 'port' child nodes according to the bindings defined > in [2]. The following are properties specific to those nodes:
Hi Andrzej Thank you for comments. On 04/18/2014 09:32 PM, Andrzej Hajda wrote: > Hi again, > > On 04/17/2014 01:53 PM, YoungJun Cho wrote: >> In case of using CPU interface panel, the relevant registers should be set. >> So this patch adds relevant dt bindings. >> >> Changelog v2: >> - Changes "samsung,sysreg-phandle" to "samsung,sysreg" >> >> Signed-off-by: YoungJun Cho <yj44.cho@samsung.com> >> Signed-off-by: Inki Dae <inki.dae@samsung.com> >> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> >> --- >> .../devicetree/bindings/video/samsung-fimd.txt | 9 +++++++++ >> 1 file changed, 9 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/video/samsung-fimd.txt b/Documentation/devicetree/bindings/video/samsung-fimd.txt >> index 2dad41b..6ea1adc 100644 >> --- a/Documentation/devicetree/bindings/video/samsung-fimd.txt >> +++ b/Documentation/devicetree/bindings/video/samsung-fimd.txt >> @@ -44,6 +44,15 @@ Optional Properties: >> - display-timings: timing settings for FIMD, as described in document [1]. >> Can be used in case timings cannot be provided otherwise >> or to override timings provided by the panel. >> +- samsung,sysreg: handle to syscon used to control the system registers >> +- vidout-i80-ldi: boolean to support i80 interface instead of rgb one >> +- cs-setup: clock cycles for the active period of address signal enable until >> + chip select is enable in i80 interface >> +- wr-setup: clock cycles for the active period of CS signal enable until >> + write signal is enable in i80 interface >> +- wr-act: clock cycles for the active period of CS enable in i80 interface >> +- wr-hold: clock cycles for the active period of CS disable until write signal >> + is disable in i80 interface > > As Laurent wrote earlier it would be good to consider providing these > properties > by panel. Panel can pass it to DSI probably via mipi_dsi_device > structure. DSI to FIMD > can use exynos drm_framework probably. > Anyway if you add optional properties please add info about default > value, ie when property > is not present. You and Laurent thought these CPU timings should be in panel. Ok, how about that vidout-i80-ldi is remained in fimd board specific DT entry and other CPU timings relevant properties are moved to panel for considering probe order? That's because the IRQ resource of fimd should be "lcd_sys" for I80 interface and decided in probe time(bind time after adopting super device node). But the fimd probe routine is prior to panel probe routine and it is also ugly that fimd parses the properties of panel DT for that. Do you have any better idea? Thank you Best regards YJ > > Regards > Andrzej > >> >> The device node can contain 'port' child nodes according to the bindings defined >> in [2]. The following are properties specific to those nodes: > >
diff --git a/Documentation/devicetree/bindings/video/samsung-fimd.txt b/Documentation/devicetree/bindings/video/samsung-fimd.txt index 2dad41b..6ea1adc 100644 --- a/Documentation/devicetree/bindings/video/samsung-fimd.txt +++ b/Documentation/devicetree/bindings/video/samsung-fimd.txt @@ -44,6 +44,15 @@ Optional Properties: - display-timings: timing settings for FIMD, as described in document [1]. Can be used in case timings cannot be provided otherwise or to override timings provided by the panel. +- samsung,sysreg: handle to syscon used to control the system registers +- vidout-i80-ldi: boolean to support i80 interface instead of rgb one +- cs-setup: clock cycles for the active period of address signal enable until + chip select is enable in i80 interface +- wr-setup: clock cycles for the active period of CS signal enable until + write signal is enable in i80 interface +- wr-act: clock cycles for the active period of CS enable in i80 interface +- wr-hold: clock cycles for the active period of CS disable until write signal + is disable in i80 interface The device node can contain 'port' child nodes according to the bindings defined in [2]. The following are properties specific to those nodes: