From patchwork Mon Apr 21 12:28:35 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: YoungJun Cho X-Patchwork-Id: 4024171 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 45C559F319 for ; Mon, 21 Apr 2014 12:28:56 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 33DDF2022D for ; Mon, 21 Apr 2014 12:28:55 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 4A2812021F for ; Mon, 21 Apr 2014 12:28:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B72F06E683; Mon, 21 Apr 2014 05:28:47 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mailout3.samsung.com (mailout3.samsung.com [203.254.224.33]) by gabe.freedesktop.org (Postfix) with ESMTP id 649F06E386 for ; Mon, 21 Apr 2014 05:28:46 -0700 (PDT) Received: from epcpsbgr4.samsung.com (u144.gpu120.samsung.co.kr [203.254.230.144]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0N4D009JARZX3K20@mailout3.samsung.com> for dri-devel@lists.freedesktop.org; Mon, 21 Apr 2014 21:28:45 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [203.254.230.43]) by epcpsbgr4.samsung.com (EPCPMTA) with SMTP id D8.E8.09952.DFE05535; Mon, 21 Apr 2014 21:28:45 +0900 (KST) X-AuditID: cbfee690-b7fcd6d0000026e0-48-53550efd0109 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 33.B3.27725.DFE05535; Mon, 21 Apr 2014 21:28:45 +0900 (KST) Received: from localhost.localdomain ([10.252.75.90]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0N4D000WURZT7I00@mmp2.samsung.com>; Mon, 21 Apr 2014 21:28:44 +0900 (KST) From: YoungJun Cho To: airlied@linux.ie, dri-devel@lists.freedesktop.org Subject: [RFC v2 PATCH 08/14] drm/exynos: dsi: add driver data to support Exynos5420 Date: Mon, 21 Apr 2014 21:28:35 +0900 Message-id: <1398083321-8668-9-git-send-email-yj44.cho@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1398083321-8668-1-git-send-email-yj44.cho@samsung.com> References: <1398083321-8668-1-git-send-email-yj44.cho@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrFIsWRmVeSWpSXmKPExsVy+t8zbd2/fKHBBttPSVrcWneO1aL33Ekm i/lHgKwrX9+zWfS/Wchqce7VSkaLSfcnsFi8uHeRxaJ3wVU2i7NNb9gtOicuYbeYcX4fk8XS 6xeZLCZMX8ti0br3CLvFyT+9jBYzJr9ks/i5ax6Lg5DHmnlrGD0u9/UyeeycdZfdY+XyL2we sztmsnpsWtXJ5nHn2h42j+3fHrB63O8+zuTRt2UVo8fnTXIB3FFcNimpOZllqUX6dglcGQcX XGArWGVYcXHjbeYGxp/qXYwcHBICJhJ32sO6GDmBTDGJC/fWs3UxcnEICSxjlDj98g4zRMJE Ys/XpawQiemMEgubXjBDOK1MEnN/bQWrYhPQlHj+cQcriC0iYCrRMWkpC4jNLLCIWWLxHSMQ W1ggTKKh9R5YnEVAVWLa4ftg9bwCzhLTj85lgrhIQWLOJBuQMKeAi8Tu6UvASoSASr40f2YE 2SshMJND4vvjPiaIOQIS3yYfYoHolZXYdADqaEmJgytusExgFF7AyLCKUTS1ILmgOCm9yESv ODG3uDQvXS85P3cTIyQeJ+xgvHfA+hBjMtC4icxSosn5wHjOK4k3NDYzsjA1MTU2Mrc0I01Y SZxX7VFSkJBAemJJanZqakFqUXxRaU5q8SFGJg5OqQbGlfoLgnc+3lgbJnLmqc+kz6mxtfs4 Z2adDzvXWrfJeJtXesz0V3Ix9y9NTPY8s3bVmVcPZYVWNV9Oa5h5IXke68P5xYzZJWKfvP2P v/ne43H3329fufJlxc4NNpnrzjwXPJsu4L/9eUV1wKI8r2DbjX0/D9g8PXVzrnCM6LRynqJ9 d7OVCgz+KLEUZyQaajEXFScCAN0y6zPdAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrBKsWRmVeSWpSXmKPExsVy+t9jQd2/fKHBBi8miVjcWneO1aL33Ekm i/lHgKwrX9+zWfS/Wchqce7VSkaLSfcnsFi8uHeRxaJ3wVU2i7NNb9gtOicuYbeYcX4fk8XS 6xeZLCZMX8ti0br3CLvFyT+9jBYzJr9ks/i5ax6Lg5DHmnlrGD0u9/UyeeycdZfdY+XyL2we sztmsnpsWtXJ5nHn2h42j+3fHrB63O8+zuTRt2UVo8fnTXIB3FENjDYZqYkpqUUKqXnJ+SmZ eem2St7B8c7xpmYGhrqGlhbmSgp5ibmptkouPgG6bpk5QM8pKZQl5pQChQISi4uV9O0wTQgN cdO1gGmM0PUNCYLrMTJAAwnrGDMOLrjAVrDKsOLixtvMDYw/1bsYOTkkBEwk9nxdygphi0lc uLeerYuRi0NIYDqjxMKmF8wQTiuTxNxfW5lBqtgENCWef9wB1iEiYCrRMWkpC4jNLLCIWWLx HSMQW1ggTKKh9R5YnEVAVWLa4ftg9bwCzhLTj85l6mLkANqmIDFnkg1ImFPARWL39CVgJUJA JV+aPzNOYORdwMiwilE0tSC5oDgpPddQrzgxt7g0L10vOT93EyM43p9J7WBc2WBxiFGAg1GJ h3dGSUiwEGtiWXFl7iFGCQ5mJRHeiPVAId6UxMqq1KL8+KLSnNTiQ4zJQEdNZJYSTc4HpqK8 knhDYxMzI0sjM2MTc2Nj0oSVxHkPtFoHCgmkJ5akZqemFqQWwWxh4uCUamBcYT3r/LQVHhv8 FFtS52ntkLU7+X7etxI+y/Ln2qK9jo3HPa7NUN15X/fe4dPvZjZUz537V45l44Wbxw92nn+2 c5LKaT/348l7WjauEA+IXPBA4IaMakvKrLV+0TePWZ6/epJn4UHGC4+nrK7dK51Q9D598cP4 V5HaakG+VgvczF5XmN6+p2L0QomlOCPRUIu5qDgRAKw+Hsk7AwAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, sachin.kamat@linaro.org, sw0312.kim@samsung.com, a.hajda@samsung.com, kyungmin.park@samsung.com, robh+dt@kernel.org, laurent.pinchart@ideasonboard.com, galak@codeaurora.org, kgene.kim@samsung.com X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The offset of register DSIM_PLLTMR_REG in Exynos5420 is different from the one in Exynos4 SoC. In case of Exynos5420 SoC, there is no frequency band bit in DSIM_PLLCTRL_REG, and it uses DSIM_PHYCTRL_REG and DSIM_PHYTIMING*_REG instead. So this patch adds driver data to distinguish it. Signed-off-by: YoungJun Cho Acked-by: Inki Dae Acked-by: Kyungmin Park --- drivers/gpu/drm/exynos/exynos_drm_dsi.c | 101 ++++++++++++++++++++++++------- 1 file changed, 80 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index 179f2fa..fcd577f 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -17,6 +17,7 @@ #include #include +#include #include #include @@ -54,9 +55,12 @@ /* FIFO memory AC characteristic register */ #define DSIM_PLLCTRL_REG 0x4c /* PLL control register */ -#define DSIM_PLLTMR_REG 0x50 /* PLL timer register */ #define DSIM_PHYACCHR_REG 0x54 /* D-PHY AC characteristic register */ #define DSIM_PHYACCHR1_REG 0x58 /* D-PHY AC characteristic register1 */ +#define DSIM_PHYCTRL_REG 0x5c +#define DSIM_PHYTIMING_REG 0x64 +#define DSIM_PHYTIMING1_REG 0x68 +#define DSIM_PHYTIMING2_REG 0x6c /* DSIM_STATUS */ #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0) @@ -233,6 +237,12 @@ struct exynos_dsi_transfer { #define DSIM_STATE_INITIALIZED BIT(1) #define DSIM_STATE_CMD_LPM BIT(2) +struct exynos_dsi_driver_data { + unsigned int plltmr_reg; + + unsigned int has_freqband:1; +}; + struct exynos_dsi { struct mipi_dsi_host dsi_host; struct drm_connector connector; @@ -262,11 +272,39 @@ struct exynos_dsi { spinlock_t transfer_lock; /* protects transfer_list */ struct list_head transfer_list; + + struct exynos_dsi_driver_data *driver_data; }; #define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host) #define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector) +static struct exynos_dsi_driver_data exynos4_dsi_driver_data = { + .plltmr_reg = 0x50, + .has_freqband = 1, +}; + +static struct exynos_dsi_driver_data exynos5_dsi_driver_data = { + .plltmr_reg = 0x58, +}; + +static struct of_device_id exynos_dsi_of_match[] = { + { .compatible = "samsung,exynos4210-mipi-dsi", + .data = &exynos4_dsi_driver_data }, + { .compatible = "samsung,exynos5420-mipi-dsi", + .data = &exynos5_dsi_driver_data }, + { } +}; + +static inline struct exynos_dsi_driver_data *exynos_dsi_get_driver_data( + struct platform_device *pdev) +{ + const struct of_device_id *of_id = + of_match_device(exynos_dsi_of_match, &pdev->dev); + + return (struct exynos_dsi_driver_data *)of_id->data; +} + static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi) { if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300))) @@ -340,14 +378,9 @@ static unsigned long exynos_dsi_pll_find_pms(struct exynos_dsi *dsi, static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi, unsigned long freq) { - static const unsigned long freq_bands[] = { - 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ, - 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ, - 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ, - 770 * MHZ, 870 * MHZ, 950 * MHZ, - }; + struct exynos_dsi_driver_data *driver_data = dsi->driver_data; unsigned long fin, fout; - int timeout, band; + int timeout; u8 p, s; u16 m; u32 reg; @@ -368,18 +401,30 @@ static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi, "failed to find PLL PMS for requested frequency\n"); return -EFAULT; } + dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s); - for (band = 0; band < ARRAY_SIZE(freq_bands); ++band) - if (fout < freq_bands[band]) - break; + writel(500, dsi->reg_base + driver_data->plltmr_reg); + + reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s); + + if (driver_data->has_freqband) { + static const unsigned long freq_bands[] = { + 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ, + 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ, + 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ, + 770 * MHZ, 870 * MHZ, 950 * MHZ, + }; + int band; - dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d), band %d\n", fout, - p, m, s, band); + for (band = 0; band < ARRAY_SIZE(freq_bands); ++band) + if (fout < freq_bands[band]) + break; - writel(500, dsi->reg_base + DSIM_PLLTMR_REG); + dev_dbg(dsi->dev, "band %d\n", band); + + reg |= DSIM_FREQ_BAND(band); + } - reg = DSIM_FREQ_BAND(band) | DSIM_PLL_EN - | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s); writel(reg, dsi->reg_base + DSIM_PLLCTRL_REG); timeout = 1000; @@ -391,6 +436,24 @@ static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi, reg = readl(dsi->reg_base + DSIM_STATUS_REG); } while ((reg & DSIM_PLL_STABLE) == 0); + if (!driver_data->has_freqband) { + /* b dphy ctrl */ + reg = 0x0af & 0x1ff; + writel(reg, dsi->reg_base + DSIM_PHYCTRL_REG); + + /* phy timing */ + reg = 0x06 << 8 | 0x0b; + writel(reg, dsi->reg_base + DSIM_PHYTIMING_REG); + + /* phy timing 1 */ + reg = 0x07 << 24 | 0x27 << 16 | 0x0d << 8 | 0x08; + writel(reg, dsi->reg_base + DSIM_PHYTIMING1_REG); + + /* phy timing 2 */ + reg = 0x09 << 16 | 0x0d << 8 | 0x0b; + writel(reg, dsi->reg_base + DSIM_PHYTIMING2_REG); + } + return fout; } @@ -1412,6 +1475,7 @@ static int exynos_dsi_probe(struct platform_device *pdev) dsi->dsi_host.dev = &pdev->dev; dsi->dev = &pdev->dev; + dsi->driver_data = exynos_dsi_get_driver_data(pdev); ret = exynos_dsi_parse_dt(dsi); if (ret) @@ -1516,11 +1580,6 @@ static const struct dev_pm_ops exynos_dsi_pm_ops = { SET_SYSTEM_SLEEP_PM_OPS(exynos_dsi_suspend, exynos_dsi_resume) }; -static struct of_device_id exynos_dsi_of_match[] = { - { .compatible = "samsung,exynos4210-mipi-dsi" }, - { } -}; - struct platform_driver dsi_driver = { .probe = exynos_dsi_probe, .remove = exynos_dsi_remove,