| Message ID | 1400815968-1084-3-git-send-email-marcheu@chromium.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, May 22, 2014 at 08:32:48PM -0700, Stéphane Marchesin wrote: > I suspect this is a copy/paste error. > > Signed-off-by: Stéphane Marchesin <marcheu@chromium.org> > --- > drivers/gpu/drm/tegra/sor.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Would you mind if I extend the commit message with something like the following: Lanes are powered up in decreasing order, so they should be powered down in increasing order. Also does this fix any issues in particular that you were seeing or is it just an "oddity" that you noticed during review? At least on Venice2 it doesn't seem to matter in what order the lanes are powered up or down. Thierry
diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index 43709ee..23fb9b1 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -740,7 +740,7 @@ static int tegra_sor_power_down(struct tegra_sor *sor) tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); /* stop lane sequencer */ - value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | + value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP | SOR_LANE_SEQ_CTL_POWER_STATE_DOWN; tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
I suspect this is a copy/paste error. Signed-off-by: Stéphane Marchesin <marcheu@chromium.org> --- drivers/gpu/drm/tegra/sor.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)