From patchwork Thu Jun 5 18:24:28 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jesse Barnes X-Patchwork-Id: 4308101 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 11CAA9F163 for ; Thu, 5 Jun 2014 18:32:56 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1329F201EC for ; Thu, 5 Jun 2014 18:32:55 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 1FA3320154 for ; Thu, 5 Jun 2014 18:32:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E40596E2C2; Thu, 5 Jun 2014 11:32:52 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org X-Greylist: delayed 400 seconds by postgrey-1.34 at gabe; Thu, 05 Jun 2014 11:32:52 PDT Received: from gproxy6-pub.mail.unifiedlayer.com (gproxy6-pub.mail.unifiedlayer.com [67.222.39.168]) by gabe.freedesktop.org (Postfix) with SMTP id 31F8B6E9AB for ; Thu, 5 Jun 2014 11:32:52 -0700 (PDT) Received: (qmail 31028 invoked by uid 0); 5 Jun 2014 18:26:12 -0000 Received: from unknown (HELO cmgw2) (10.0.90.83) by gproxy6.mail.unifiedlayer.com with SMTP; 5 Jun 2014 18:26:12 -0000 Received: from box514.bluehost.com ([74.220.219.114]) by cmgw2 with id AiS31o00v2UhLwi01iS6xK; Thu, 05 Jun 2014 12:26:11 -0600 X-Authority-Analysis: v=2.1 cv=Q9RBveGa c=1 sm=1 tr=0 a=9W6Fsu4pMcyimqnCr1W0/w==:117 a=9W6Fsu4pMcyimqnCr1W0/w==:17 a=cNaOj0WVAAAA:8 a=f5113yIGAAAA:8 a=1t57F9VvtZEA:10 a=3ROhxo7VqVMA:10 a=IkcTkHD0fZMA:10 a=TBVoxVdAAAAA:8 a=GhZ5P8ky69gA:10 a=noBwr2J6l1kA:10 a=pGLkceISAAAA:8 a=4ofp4RG3rb6FPLkiIzwA:9 a=fsBa0HF9RVKvB_vX:21 a=j-qDzOi6_jRG9jQC:21 a=QEXdDO2ut3YA:10 a=MSl-tDqOz04A:10 a=rW6DTWptwo0A:10 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=virtuousgeek.org; s=default; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=7oF5qoIg316IgTH/RhVxSdz1bhkW/s2zC0W9bmUpNpg=; b=tiUdj0BrfXtkEsux/5LQdCfwlxJ8RtxFGUsZEX0yJ1S/S79sSFK85mQt7LL+WtIAL9gXazv1CA17R+RfsxpohQ7jD1VU0Zbsfr45QCzrpMFr6rDJl807NZzqMmVdrKvX; Received: from [67.161.37.189] (port=60655 helo=localhost.localdomain) by box514.bluehost.com with esmtpsa (TLSv1.1:DHE-RSA-AES256-SHA:256) (Exim 4.82) (envelope-from ) id 1WscMW-0001x8-Dd; Thu, 05 Jun 2014 12:26:04 -0600 From: Jesse Barnes To: intel-gfx@lists.freedesktop.org Subject: [PATCH 2/5] drm/i915: preserve swizzle settings if necessary v3 Date: Thu, 5 Jun 2014 11:24:28 -0700 Message-Id: <1401992671-2548-2-git-send-email-jbarnes@virtuousgeek.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1401992671-2548-1-git-send-email-jbarnes@virtuousgeek.org> References: <1401992671-2548-1-git-send-email-jbarnes@virtuousgeek.org> MIME-Version: 1.0 X-Identified-User: {10642:box514.bluehost.com:virtuous:virtuousgeek.org} {sentby:smtp auth 67.161.37.189 authed with jbarnes@virtuousgeek.org} Cc: dri-devel@lists.freedesktop.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some machines (like MBAs) might use a tiled framebuffer but not enable display swizzling at boot time. We want to preserve that configuration if possible to prevent a boot time mode set. On IVB+ it shouldn't affect performance anyway since the memory controller does internal swizzling anyway. For most other configs we'll be able to enable swizzling at boot time, since the initial framebuffer won't be tiled, thus we won't see any corruption when we enable it. v2: preserve swizzling if BIOS had it set (Daniel) v3: preserve swizzling only if we inherited a tiled framebuffer (Daniel) check display swizzle setting in detect_bit_6_swizzle (Daniel) use gen6 as cutoff point (Daniel) Reported-by: Kristian Høgsberg Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gem.c | 3 +++ drivers/gpu/drm/i915/i915_gem_tiling.c | 38 +++++++++++++++++++--------------- drivers/gpu/drm/i915/intel_display.c | 3 +++ 4 files changed, 28 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index f57b752..f49fdcb 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1405,6 +1405,7 @@ struct drm_i915_private { struct intel_vbt_data vbt; bool bios_ssc; /* BIOS had SSC enabled at boot? */ + bool preserve_bios_swizzle; /* overlay */ struct intel_overlay *overlay; diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index bfc7af0..0b168fb 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4580,6 +4580,9 @@ void i915_gem_init_swizzling(struct drm_device *dev) dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) return; + if (INTEL_INFO(dev)->gen >= 6 && dev_priv->preserve_bios_swizzle) + return; + I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | DISP_TILE_SURFACE_SWIZZLING); diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c index cb150e8..73005ad 100644 --- a/drivers/gpu/drm/i915/i915_gem_tiling.c +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c @@ -91,26 +91,30 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; - if (IS_VALLEYVIEW(dev)) { - swizzle_x = I915_BIT_6_SWIZZLE_NONE; - swizzle_y = I915_BIT_6_SWIZZLE_NONE; - } else if (INTEL_INFO(dev)->gen >= 6) { + if (INTEL_INFO(dev)->gen >= 6) { uint32_t dimm_c0, dimm_c1; - dimm_c0 = I915_READ(MAD_DIMM_C0); - dimm_c1 = I915_READ(MAD_DIMM_C1); - dimm_c0 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK; - dimm_c1 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK; - /* Enable swizzling when the channels are populated with - * identically sized dimms. We don't need to check the 3rd - * channel because no cpu with gpu attached ships in that - * configuration. Also, swizzling only makes sense for 2 - * channels anyway. */ - if (dimm_c0 == dimm_c1) { - swizzle_x = I915_BIT_6_SWIZZLE_9_10; - swizzle_y = I915_BIT_6_SWIZZLE_9; - } else { + + /* Make sure to honor boot time display configuration */ + if (!(I915_READ(DISP_ARB_CTL) & DISP_TILE_SURFACE_SWIZZLING)) { swizzle_x = I915_BIT_6_SWIZZLE_NONE; swizzle_y = I915_BIT_6_SWIZZLE_NONE; + } else { + dimm_c0 = I915_READ(MAD_DIMM_C0); + dimm_c1 = I915_READ(MAD_DIMM_C1); + dimm_c0 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK; + dimm_c1 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK; + /* Enable swizzling when the channels are populated with + * identically sized dimms. We don't need to check the + * 3rd channel because no cpu with gpu attached ships + * in that configuration. Also, swizzling only makes + * sense for 2 channels anyway. */ + if (dimm_c0 == dimm_c1) { + swizzle_x = I915_BIT_6_SWIZZLE_9_10; + swizzle_y = I915_BIT_6_SWIZZLE_9; + } else { + swizzle_x = I915_BIT_6_SWIZZLE_NONE; + swizzle_y = I915_BIT_6_SWIZZLE_NONE; + } } } else if (IS_GEN5(dev)) { /* On Ironlake whatever DRAM config, GPU always do diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 0e8c9bc..7dbbef7 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2361,6 +2361,7 @@ static void intel_find_plane_obj(struct intel_crtc *intel_crtc, struct intel_plane_config *plane_config) { struct drm_device *dev = intel_crtc->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; struct drm_crtc *c; struct intel_crtc *i; struct intel_framebuffer *fb; @@ -2389,6 +2390,8 @@ static void intel_find_plane_obj(struct intel_crtc *intel_crtc, fb = to_intel_framebuffer(c->primary->fb); if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) { + if (fb->obj->tiling_mode != I915_TILING_NONE) + dev_priv->preserve_bios_swizzle = true; drm_framebuffer_reference(c->primary->fb); intel_crtc->base.primary->fb = c->primary->fb; break;