From patchwork Thu Jul 10 21:50:16 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oded Gabbay X-Patchwork-Id: 4528211 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 8597A9F37C for ; Thu, 10 Jul 2014 23:33:34 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 84CE620204 for ; Thu, 10 Jul 2014 23:33:33 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 8ADEE2011D for ; Thu, 10 Jul 2014 23:33:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 824F86E798; Thu, 10 Jul 2014 16:33:15 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wi0-f170.google.com (mail-wi0-f170.google.com [209.85.212.170]) by gabe.freedesktop.org (Postfix) with ESMTP id 87DFD6E163 for ; Thu, 10 Jul 2014 14:51:57 -0700 (PDT) Received: by mail-wi0-f170.google.com with SMTP id cc10so5147775wib.1 for ; Thu, 10 Jul 2014 14:51:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xE2sbbHtwWa1JV0JQU5jLSI79GMIxGe6oylqNcStqg8=; b=l+tw1L/pb1N468k9fllkNeb3Ixx/40mVQR6LaAc7PVBvY3mxFglIC4eeoZvwZEjsbu WSbMwyMW3GNBJLGyQOX+LYWiRsOkwEDyxx5byMCvmrFPno3GT04VBcoQTsPMXRVQFI3j SJSwE0nXasG9QcVClnv5fL6Wt6iNyRc7JwE4gSTJoqmwufTYmVSvsKeUgtBkpdotJuKn EJZH0lJBP4AmFzAhbmlkLLpdCiBP/uLsuPEV5RnOCNUASImryRdIV4toAfDm/8La8wRY qEidzuZ2Hrdt5hcHCnzuae4mviERDSk3RbL5ory3ZKf09e5kG36XSEexbjJhMhDUW6G5 PKMg== X-Received: by 10.180.198.116 with SMTP id jb20mr139734wic.59.1405029116829; Thu, 10 Jul 2014 14:51:56 -0700 (PDT) Received: from localhost.localdomain ([77.127.59.49]) by mx.google.com with ESMTPSA id n2sm805353wjf.40.2014.07.10.14.51.54 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 10 Jul 2014 14:51:56 -0700 (PDT) From: Oded Gabbay X-Google-Original-From: Oded Gabbay To: David Airlie , Alex Deucher , Jerome Glisse Subject: [PATCH 16/83] hsa/radeon: Add the isr function of the KFD scehduler Date: Fri, 11 Jul 2014 00:50:16 +0300 Message-Id: <1405029027-6085-15-git-send-email-oded.gabbay@amd.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1405029027-6085-1-git-send-email-oded.gabbay@amd.com> References: <1405029027-6085-1-git-send-email-oded.gabbay@amd.com> X-Mailman-Approved-At: Thu, 10 Jul 2014 16:33:12 -0700 Cc: Andrew Lewycky , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.0 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RCVD_IN_SORBS_WEB, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the isr function to the KFD scheduler code. This function us called from the kgd2kfd_interrupt function which is an interrupt-context function. The purpose of the isr function is to determine whether the interrupt that arrived is interesting, i.e. some action need to be taken. Signed-off-by: Oded Gabbay --- drivers/gpu/hsa/radeon/cik_int.h | 50 ++++++++++++++++++++++++ drivers/gpu/hsa/radeon/cik_regs.h | 2 + drivers/gpu/hsa/radeon/kfd_sched_cik_static.c | 56 +++++++++++++++++++++++++++ 3 files changed, 108 insertions(+) create mode 100644 drivers/gpu/hsa/radeon/cik_int.h diff --git a/drivers/gpu/hsa/radeon/cik_int.h b/drivers/gpu/hsa/radeon/cik_int.h new file mode 100644 index 0000000..e98551d --- /dev/null +++ b/drivers/gpu/hsa/radeon/cik_int.h @@ -0,0 +1,50 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef HSA_RADEON_CIK_INT_H_INCLUDED +#define HSA_RADEON_CIK_INT_H_INCLUDED + +#include + +struct cik_ih_ring_entry { + uint32_t source_id : 8; + uint32_t reserved1 : 8; + uint32_t reserved2 : 16; + + uint32_t data : 28; + uint32_t reserved3 : 4; + + /* pipeid, meid and unused3 are officially called RINGID, + * but for our purposes, they always decode into pipe and ME. */ + uint32_t pipeid : 2; + uint32_t meid : 2; + uint32_t reserved4 : 4; + uint32_t vmid : 8; + uint32_t pasid : 16; + + uint32_t reserved5; +}; + +#define CIK_INTSRC_DEQUEUE_COMPLETE 0xC6 + +#endif + diff --git a/drivers/gpu/hsa/radeon/cik_regs.h b/drivers/gpu/hsa/radeon/cik_regs.h index d0cdc57..ef1d7ab 100644 --- a/drivers/gpu/hsa/radeon/cik_regs.h +++ b/drivers/gpu/hsa/radeon/cik_regs.h @@ -23,6 +23,8 @@ #ifndef CIK_REGS_H #define CIK_REGS_H +#define IH_VMID_0_LUT 0x3D40u + #define BIF_DOORBELL_CNTL 0x530Cu #define SRBM_GFX_CNTL 0xE44 diff --git a/drivers/gpu/hsa/radeon/kfd_sched_cik_static.c b/drivers/gpu/hsa/radeon/kfd_sched_cik_static.c index b986ff9..f86f958 100644 --- a/drivers/gpu/hsa/radeon/kfd_sched_cik_static.c +++ b/drivers/gpu/hsa/radeon/kfd_sched_cik_static.c @@ -25,9 +25,12 @@ #include #include #include +#include +#include #include "kfd_priv.h" #include "kfd_scheduler.h" #include "cik_regs.h" +#include "cik_int.h" /* CIK CP hardware is arranged with 8 queues per pipe and 8 pipes per MEC (microengine for compute). * The first MEC is ME 1 with the GFX ME as ME 0. @@ -273,6 +276,8 @@ static void set_vmid_pasid_mapping(struct cik_static_private *priv, unsigned int while (!(READ_REG(priv->dev, ATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid))) cpu_relax(); WRITE_REG(priv->dev, ATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid); + + WRITE_REG(priv->dev, IH_VMID_0_LUT + vmid*sizeof(uint32_t), pasid); } static uint32_t compute_sh_mem_bases_64bit(unsigned int top_address_nybble) @@ -786,6 +791,54 @@ cik_static_destroy_queue(struct kfd_scheduler *scheduler, struct kfd_scheduler_q release_hqd(priv, hwq->queue); } +/* Figure out the KFD compute pipe ID for an interrupt ring entry. + * Returns true if it's a KFD compute pipe, false otherwise. */ +static bool int_compute_pipe(const struct cik_static_private *priv, + const struct cik_ih_ring_entry *ih_ring_entry, + uint32_t *kfd_pipe) +{ + uint32_t pipe_id; + + if (ih_ring_entry->meid == 0) /* Ignore graphics interrupts - compute only. */ + return false; + + pipe_id = (ih_ring_entry->meid - 1) * CIK_PIPES_PER_MEC + ih_ring_entry->pipeid; + if (pipe_id < priv->first_pipe) + return false; + + pipe_id -= priv->first_pipe; + + *kfd_pipe = pipe_id; + + return true; +} + +static bool +cik_static_interrupt_isr(struct kfd_scheduler *scheduler, const void *ih_ring_entry) +{ + struct cik_static_private *priv = kfd_scheduler_to_private(scheduler); + const struct cik_ih_ring_entry *ihre = ih_ring_entry; + uint32_t source_id = ihre->source_id; + uint32_t pipe_id; + + /* We only care about CP interrupts here, they all come with a pipe. */ + if (!int_compute_pipe(priv, ihre, &pipe_id)) + return false; + + dev_info(radeon_kfd_chardev(), "INT(ISR): src=%02x, data=0x%x, pipe=%u, vmid=%u, pasid=%u\n", + ihre->source_id, ihre->data, pipe_id, ihre->vmid, ihre->pasid); + + switch (source_id) { + default: + return false; /* Not interested. */ + } +} + +static void +cik_static_interrupt_wq(struct kfd_scheduler *scheduler, const void *ih_ring_entry) +{ +} + const struct kfd_scheduler_class radeon_kfd_cik_static_scheduler_class = { .name = "CIK static scheduler", .create = cik_static_create, @@ -797,4 +850,7 @@ const struct kfd_scheduler_class radeon_kfd_cik_static_scheduler_class = { .queue_size = sizeof(struct cik_static_queue), .create_queue = cik_static_create_queue, .destroy_queue = cik_static_destroy_queue, + + .interrupt_isr = cik_static_interrupt_isr, + .interrupt_wq = cik_static_interrupt_wq, };