| Message ID | 1406799831-2502-5-git-send-email-michel@daenzer.net (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Am 31.07.2014 um 11:43 schrieb Michel Dänzer: > From: Michel Dänzer <michel.daenzer@amd.com> > > Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> At least for PIPE_USAGE_STREAM buffers that's a bad idea, cause they are used by VDPAU to read back to data to a CPU buffer and that's really slow from VRAM. Christian. > --- > src/gallium/drivers/radeon/r600_buffer_common.c | 15 +++++++++++---- > 1 file changed, 11 insertions(+), 4 deletions(-) > > diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c b/src/gallium/drivers/radeon/r600_buffer_common.c > index 154c33d..d747cbc 100644 > --- a/src/gallium/drivers/radeon/r600_buffer_common.c > +++ b/src/gallium/drivers/radeon/r600_buffer_common.c > @@ -110,14 +110,21 @@ bool r600_init_resource(struct r600_common_screen *rscreen, > enum radeon_bo_flag flags = 0; > > switch (res->b.b.usage) { > - case PIPE_USAGE_DYNAMIC: > - case PIPE_USAGE_STREAM: > - flags = RADEON_FLAG_GTT_WC; > - /* fall through */ > case PIPE_USAGE_STAGING: > /* Transfers are likely to occur more often with these resources. */ > res->domains = RADEON_DOMAIN_GTT; > break; > + case PIPE_USAGE_STREAM: > + case PIPE_USAGE_DYNAMIC: > + /* Older kernels didn't always flush the HDP cache before > + * CS execution > + */ > + if (rscreen->info.drm_minor < 40) { > + res->domains = RADEON_DOMAIN_GTT; > + flags = RADEON_FLAG_GTT_WC; > + break; > + } > + /* fall through */ > case PIPE_USAGE_DEFAULT: > case PIPE_USAGE_IMMUTABLE: > default:
On 31.07.2014 18:52, Christian König wrote: > Am 31.07.2014 um 11:43 schrieb Michel Dänzer: >> From: Michel Dänzer <michel.daenzer@amd.com> >> >> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> > > At least for PIPE_USAGE_STREAM buffers that's a bad idea, cause they are > used by VDPAU to read back to data to a CPU buffer and that's really > slow from VRAM. From src/gallium/docs/source/screen.rst: * ``PIPE_USAGE_DEFAULT``: Optimized for fast GPU access. * ``PIPE_USAGE_IMMUTABLE``: Optimized for fast GPU access and the resource is not expected to be mapped or changed (even by the GPU) after the first upload. * ``PIPE_USAGE_DYNAMIC``: Expect frequent write-only CPU access. What is uploaded is expected to be used at least several times by the GPU. * ``PIPE_USAGE_STREAM``: Expect frequent write-only CPU access. What is uploaded is expected to be used only once by the GPU. * ``PIPE_USAGE_STAGING``: Optimized for fast CPU access. That reads to me like only PIPE_USAGE_STAGING is expected to provide fast CPU reads.
Am 31.07.2014 um 11:57 schrieb Michel Dänzer: > On 31.07.2014 18:52, Christian König wrote: >> Am 31.07.2014 um 11:43 schrieb Michel Dänzer: >>> From: Michel Dänzer <michel.daenzer@amd.com> >>> >>> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> >> At least for PIPE_USAGE_STREAM buffers that's a bad idea, cause they are >> used by VDPAU to read back to data to a CPU buffer and that's really >> slow from VRAM. > From src/gallium/docs/source/screen.rst: > > * ``PIPE_USAGE_DEFAULT``: Optimized for fast GPU access. > * ``PIPE_USAGE_IMMUTABLE``: Optimized for fast GPU access and the resource is > not expected to be mapped or changed (even by the GPU) after the first upload. > * ``PIPE_USAGE_DYNAMIC``: Expect frequent write-only CPU access. What is > uploaded is expected to be used at least several times by the GPU. > * ``PIPE_USAGE_STREAM``: Expect frequent write-only CPU access. What is > uploaded is expected to be used only once by the GPU. > * ``PIPE_USAGE_STAGING``: Optimized for fast CPU access. > > That reads to me like only PIPE_USAGE_STAGING is expected to provide fast > CPU reads. Forget what I've wrote, we do this handling by letting the driver copy the bitmap content to a staging texture. All other use case indeed use PIPE_USAGE_STAGING. Christian.
Reviewed-by: Marek Olšák <marek.olsak@amd.com> Marek On Thu, Jul 31, 2014 at 11:43 AM, Michel Dänzer <michel@daenzer.net> wrote: > From: Michel Dänzer <michel.daenzer@amd.com> > > Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> > --- > src/gallium/drivers/radeon/r600_buffer_common.c | 15 +++++++++++---- > 1 file changed, 11 insertions(+), 4 deletions(-) > > diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c b/src/gallium/drivers/radeon/r600_buffer_common.c > index 154c33d..d747cbc 100644 > --- a/src/gallium/drivers/radeon/r600_buffer_common.c > +++ b/src/gallium/drivers/radeon/r600_buffer_common.c > @@ -110,14 +110,21 @@ bool r600_init_resource(struct r600_common_screen *rscreen, > enum radeon_bo_flag flags = 0; > > switch (res->b.b.usage) { > - case PIPE_USAGE_DYNAMIC: > - case PIPE_USAGE_STREAM: > - flags = RADEON_FLAG_GTT_WC; > - /* fall through */ > case PIPE_USAGE_STAGING: > /* Transfers are likely to occur more often with these resources. */ > res->domains = RADEON_DOMAIN_GTT; > break; > + case PIPE_USAGE_STREAM: > + case PIPE_USAGE_DYNAMIC: > + /* Older kernels didn't always flush the HDP cache before > + * CS execution > + */ > + if (rscreen->info.drm_minor < 40) { > + res->domains = RADEON_DOMAIN_GTT; > + flags = RADEON_FLAG_GTT_WC; > + break; > + } > + /* fall through */ > case PIPE_USAGE_DEFAULT: > case PIPE_USAGE_IMMUTABLE: > default: > -- > 2.0.1 > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/dri-devel
diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c b/src/gallium/drivers/radeon/r600_buffer_common.c index 154c33d..d747cbc 100644 --- a/src/gallium/drivers/radeon/r600_buffer_common.c +++ b/src/gallium/drivers/radeon/r600_buffer_common.c @@ -110,14 +110,21 @@ bool r600_init_resource(struct r600_common_screen *rscreen, enum radeon_bo_flag flags = 0; switch (res->b.b.usage) { - case PIPE_USAGE_DYNAMIC: - case PIPE_USAGE_STREAM: - flags = RADEON_FLAG_GTT_WC; - /* fall through */ case PIPE_USAGE_STAGING: /* Transfers are likely to occur more often with these resources. */ res->domains = RADEON_DOMAIN_GTT; break; + case PIPE_USAGE_STREAM: + case PIPE_USAGE_DYNAMIC: + /* Older kernels didn't always flush the HDP cache before + * CS execution + */ + if (rscreen->info.drm_minor < 40) { + res->domains = RADEON_DOMAIN_GTT; + flags = RADEON_FLAG_GTT_WC; + break; + } + /* fall through */ case PIPE_USAGE_DEFAULT: case PIPE_USAGE_IMMUTABLE: default: