| Message ID | 1409208961-7322-1-git-send-email-michel@daenzer.net (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Am 28.08.2014 um 08:56 schrieb Michel Dänzer: > From: Michel Dänzer <michel.daenzer@amd.com> > > This flag is a hint that userspace expects the BO to be accessed by the > CPU. We can use that hint to prevent such BOs from ever being stored in > the CPU inaccessible part of VRAM. > > Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> This patch is Reviewed-by: Christian König <christian.koenig@amd.com> I think we need a similar negative flags as well, e.g. RADEON_GEM_NO_CPU_ACCESS. This way we can stop forcing buffers into the visible VRAM while pinning them for scanout. Regards, Christian. > --- > drivers/gpu/drm/radeon/radeon_object.c | 11 +++++++++-- > include/uapi/drm/radeon_drm.h | 2 ++ > 2 files changed, 11 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c > index dc74cc5..908ea541 100644 > --- a/drivers/gpu/drm/radeon/radeon_object.c > +++ b/drivers/gpu/drm/radeon/radeon_object.c > @@ -143,7 +143,12 @@ void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) > > for (i = 0; i < c; ++i) { > rbo->placements[i].fpfn = 0; > - rbo->placements[i].lpfn = 0; > + if ((rbo->flags & RADEON_GEM_CPU_ACCESS) && > + (rbo->placements[i].flags & TTM_PL_FLAG_VRAM)) > + rbo->placements[i].lpfn = > + rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; > + else > + rbo->placements[i].lpfn = 0; > } > > /* > @@ -151,7 +156,9 @@ void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) > * improve fragmentation quality. > * 512kb was measured as the most optimal number. > */ > - if (rbo->tbo.mem.size > 512 * 1024) { > + if (!((rbo->flags & RADEON_GEM_CPU_ACCESS) && > + (rbo->placements[i].flags & TTM_PL_FLAG_VRAM)) && > + rbo->tbo.mem.size > 512 * 1024) { > for (i = 0; i < c; i++) { > rbo->placements[i].flags |= TTM_PL_FLAG_TOPDOWN; > } > diff --git a/include/uapi/drm/radeon_drm.h b/include/uapi/drm/radeon_drm.h > index 509b2d7..bf0067b 100644 > --- a/include/uapi/drm/radeon_drm.h > +++ b/include/uapi/drm/radeon_drm.h > @@ -799,6 +799,8 @@ struct drm_radeon_gem_info { > #define RADEON_GEM_NO_BACKING_STORE (1 << 0) > #define RADEON_GEM_GTT_UC (1 << 1) > #define RADEON_GEM_GTT_WC (1 << 2) > +/* BO is expected to be accessed by the CPU */ > +#define RADEON_GEM_CPU_ACCESS (1 << 3) > > struct drm_radeon_gem_create { > uint64_t size;
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c index dc74cc5..908ea541 100644 --- a/drivers/gpu/drm/radeon/radeon_object.c +++ b/drivers/gpu/drm/radeon/radeon_object.c @@ -143,7 +143,12 @@ void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) for (i = 0; i < c; ++i) { rbo->placements[i].fpfn = 0; - rbo->placements[i].lpfn = 0; + if ((rbo->flags & RADEON_GEM_CPU_ACCESS) && + (rbo->placements[i].flags & TTM_PL_FLAG_VRAM)) + rbo->placements[i].lpfn = + rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; + else + rbo->placements[i].lpfn = 0; } /* @@ -151,7 +156,9 @@ void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) * improve fragmentation quality. * 512kb was measured as the most optimal number. */ - if (rbo->tbo.mem.size > 512 * 1024) { + if (!((rbo->flags & RADEON_GEM_CPU_ACCESS) && + (rbo->placements[i].flags & TTM_PL_FLAG_VRAM)) && + rbo->tbo.mem.size > 512 * 1024) { for (i = 0; i < c; i++) { rbo->placements[i].flags |= TTM_PL_FLAG_TOPDOWN; } diff --git a/include/uapi/drm/radeon_drm.h b/include/uapi/drm/radeon_drm.h index 509b2d7..bf0067b 100644 --- a/include/uapi/drm/radeon_drm.h +++ b/include/uapi/drm/radeon_drm.h @@ -799,6 +799,8 @@ struct drm_radeon_gem_info { #define RADEON_GEM_NO_BACKING_STORE (1 << 0) #define RADEON_GEM_GTT_UC (1 << 1) #define RADEON_GEM_GTT_WC (1 << 2) +/* BO is expected to be accessed by the CPU */ +#define RADEON_GEM_CPU_ACCESS (1 << 3) struct drm_radeon_gem_create { uint64_t size;