diff mbox

drm/radeon: Disable HDP flush before every CS again for < r600

Message ID 1410938755-19260-1-git-send-email-michel@daenzer.net (mailing list archive)
State New, archived
Headers show

Commit Message

Michel Dänzer Sept. 17, 2014, 7:25 a.m. UTC 
From: Michel Dänzer <michel.daenzer@amd.com>

It was causing display corruption with R300 generation GPUs at least.

Reported-and-Tested-by: Mikael Pettersson <mikpelinux@gmail.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
---
 drivers/gpu/drm/radeon/r100.c        | 28 ++++++++++++++--------------
 drivers/gpu/drm/radeon/radeon_asic.c |  2 --
 drivers/gpu/drm/radeon/radeon_asic.h |  3 +--
 drivers/gpu/drm/radeon/radeon_drv.c  |  2 +-
 4 files changed, 16 insertions(+), 19 deletions(-)

Comments

Alex Deucher Sept. 17, 2014, 1:25 p.m. UTC | #1 
On Wed, Sep 17, 2014 at 3:25 AM, Michel Dänzer <michel@daenzer.net> wrote:
> From: Michel Dänzer <michel.daenzer@amd.com>
>
> It was causing display corruption with R300 generation GPUs at least.
>
> Reported-and-Tested-by: Mikael Pettersson <mikpelinux@gmail.com>
> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>


Applied to my fixes tree.

thanks!

Alex

> ---
>  drivers/gpu/drm/radeon/r100.c        | 28 ++++++++++++++--------------
>  drivers/gpu/drm/radeon/radeon_asic.c |  2 --
>  drivers/gpu/drm/radeon/radeon_asic.h |  3 +--
>  drivers/gpu/drm/radeon/radeon_drv.c  |  2 +-
>  4 files changed, 16 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
> index 4c5ec44..b0098e7 100644
> --- a/drivers/gpu/drm/radeon/r100.c
> +++ b/drivers/gpu/drm/radeon/r100.c
> @@ -821,6 +821,20 @@ u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
>                 return RREG32(RADEON_CRTC2_CRNT_FRAME);
>  }
>
> +/**
> + * r100_ring_hdp_flush - flush Host Data Path via the ring buffer
> + * rdev: radeon device structure
> + * ring: ring buffer struct for emitting packets
> + */
> +static void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring)
> +{
> +       radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
> +       radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
> +                               RADEON_HDP_READ_BUFFER_INVALIDATE);
> +       radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
> +       radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
> +}
> +
>  /* Who ever call radeon_fence_emit should call ring_lock and ask
>   * for enough space (today caller are ib schedule and buffer move) */
>  void r100_fence_ring_emit(struct radeon_device *rdev,
> @@ -1056,20 +1070,6 @@ void r100_gfx_set_wptr(struct radeon_device *rdev,
>         (void)RREG32(RADEON_CP_RB_WPTR);
>  }
>
> -/**
> - * r100_ring_hdp_flush - flush Host Data Path via the ring buffer
> - * rdev: radeon device structure
> - * ring: ring buffer struct for emitting packets
> - */
> -void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring)
> -{
> -       radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
> -       radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
> -                               RADEON_HDP_READ_BUFFER_INVALIDATE);
> -       radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
> -       radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
> -}
> -
>  static void r100_cp_load_microcode(struct radeon_device *rdev)
>  {
>         const __be32 *fw_data;
> diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
> index eeeeabe..2dd5847 100644
> --- a/drivers/gpu/drm/radeon/radeon_asic.c
> +++ b/drivers/gpu/drm/radeon/radeon_asic.c
> @@ -185,7 +185,6 @@ static struct radeon_asic_ring r100_gfx_ring = {
>         .get_rptr = &r100_gfx_get_rptr,
>         .get_wptr = &r100_gfx_get_wptr,
>         .set_wptr = &r100_gfx_set_wptr,
> -       .hdp_flush = &r100_ring_hdp_flush,
>  };
>
>  static struct radeon_asic r100_asic = {
> @@ -332,7 +331,6 @@ static struct radeon_asic_ring r300_gfx_ring = {
>         .get_rptr = &r100_gfx_get_rptr,
>         .get_wptr = &r100_gfx_get_wptr,
>         .set_wptr = &r100_gfx_set_wptr,
> -       .hdp_flush = &r100_ring_hdp_flush,
>  };
>
>  static struct radeon_asic r300_asic = {
> diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
> index 275a5dc..7756bc1 100644
> --- a/drivers/gpu/drm/radeon/radeon_asic.h
> +++ b/drivers/gpu/drm/radeon/radeon_asic.h
> @@ -148,8 +148,7 @@ u32 r100_gfx_get_wptr(struct radeon_device *rdev,
>                       struct radeon_ring *ring);
>  void r100_gfx_set_wptr(struct radeon_device *rdev,
>                        struct radeon_ring *ring);
> -void r100_ring_hdp_flush(struct radeon_device *rdev,
> -                        struct radeon_ring *ring);
> +
>  /*
>   * r200,rv250,rs300,rv280
>   */
> diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
> index a773830..ef5b60a 100644
> --- a/drivers/gpu/drm/radeon/radeon_drv.c
> +++ b/drivers/gpu/drm/radeon/radeon_drv.c
> @@ -83,7 +83,7 @@
>   *            CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
>   *   2.39.0 - Add INFO query for number of active CUs
>   *   2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
> - *            CS to GPU
> + *            CS to GPU on >= r600
>   */
>  #define KMS_DRIVER_MAJOR       2
>  #define KMS_DRIVER_MINOR       40
> --
> 2.1.0
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
diff mbox

Patch

diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 4c5ec44..b0098e7 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -821,6 +821,20 @@  u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
 		return RREG32(RADEON_CRTC2_CRNT_FRAME);
 }
 
+/**
+ * r100_ring_hdp_flush - flush Host Data Path via the ring buffer
+ * rdev: radeon device structure
+ * ring: ring buffer struct for emitting packets
+ */
+static void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring)
+{
+	radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
+	radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
+				RADEON_HDP_READ_BUFFER_INVALIDATE);
+	radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
+	radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
+}
+
 /* Who ever call radeon_fence_emit should call ring_lock and ask
  * for enough space (today caller are ib schedule and buffer move) */
 void r100_fence_ring_emit(struct radeon_device *rdev,
@@ -1056,20 +1070,6 @@  void r100_gfx_set_wptr(struct radeon_device *rdev,
 	(void)RREG32(RADEON_CP_RB_WPTR);
 }
 
-/**
- * r100_ring_hdp_flush - flush Host Data Path via the ring buffer
- * rdev: radeon device structure
- * ring: ring buffer struct for emitting packets
- */
-void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring)
-{
-	radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
-	radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
-				RADEON_HDP_READ_BUFFER_INVALIDATE);
-	radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
-	radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
-}
-
 static void r100_cp_load_microcode(struct radeon_device *rdev)
 {
 	const __be32 *fw_data;
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index eeeeabe..2dd5847 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -185,7 +185,6 @@  static struct radeon_asic_ring r100_gfx_ring = {
 	.get_rptr = &r100_gfx_get_rptr,
 	.get_wptr = &r100_gfx_get_wptr,
 	.set_wptr = &r100_gfx_set_wptr,
-	.hdp_flush = &r100_ring_hdp_flush,
 };
 
 static struct radeon_asic r100_asic = {
@@ -332,7 +331,6 @@  static struct radeon_asic_ring r300_gfx_ring = {
 	.get_rptr = &r100_gfx_get_rptr,
 	.get_wptr = &r100_gfx_get_wptr,
 	.set_wptr = &r100_gfx_set_wptr,
-	.hdp_flush = &r100_ring_hdp_flush,
 };
 
 static struct radeon_asic r300_asic = {
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index 275a5dc..7756bc1 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -148,8 +148,7 @@  u32 r100_gfx_get_wptr(struct radeon_device *rdev,
 		      struct radeon_ring *ring);
 void r100_gfx_set_wptr(struct radeon_device *rdev,
 		       struct radeon_ring *ring);
-void r100_ring_hdp_flush(struct radeon_device *rdev,
-			 struct radeon_ring *ring);
+
 /*
  * r200,rv250,rs300,rv280
  */
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index a773830..ef5b60a 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -83,7 +83,7 @@ 
  *            CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
  *   2.39.0 - Add INFO query for number of active CUs
  *   2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
- *            CS to GPU
+ *            CS to GPU on >= r600
  */
 #define KMS_DRIVER_MAJOR	2
 #define KMS_DRIVER_MINOR	40