From patchwork Wed Oct 1 15:38:20 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Deucher X-Patchwork-Id: 5015841 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 2728DBEEA7 for ; Thu, 2 Oct 2014 04:02:01 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 63F5020165 for ; Thu, 2 Oct 2014 04:02:00 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 7E40920200 for ; Thu, 2 Oct 2014 04:01:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A17C56FA9D; Wed, 1 Oct 2014 20:57:55 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-qg0-f47.google.com (mail-qg0-f47.google.com [209.85.192.47]) by gabe.freedesktop.org (Postfix) with ESMTP id 0C1446E2A6 for ; Wed, 1 Oct 2014 08:38:42 -0700 (PDT) Received: by mail-qg0-f47.google.com with SMTP id i50so463905qgf.6 for ; Wed, 01 Oct 2014 08:38:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1XtyP/1GmrLMbNJK9+AKvxIFl3imF7t+RBScoRd4XQU=; b=lbTrx+OkvncvgCPRGOjw7oewZfUUWmLxae4Ed7UHMTkROLiqcZupjFbhoNp8WFMXzZ sxVi7HYYosgrBnM/a7dG/mhIKoVk3IFuhX0iIhbb24uW4qvjqOz8pxxkssmtJtvb1QFr 7dGs53o0Zfh34+ZW24q2AmNBhhpPKpEujpk1fH3TkyHitXzHbp9ZQeFYIb3tzADqBLw+ fUSnCVs2ptSXT1YmGeT79g9DTgQDRFv9498faXC+aqtEl+NOPqsoMBKD3d9FXO1cpzW6 T/sAOw7AKqWS68iXoXxyzhNfXWV6mNnQGsAJvEmSQS/pW3Pj2YCCC/fkT944MP8jRV4g 14tw== X-Received: by 10.224.60.129 with SMTP id p1mr25194282qah.99.1412177922644; Wed, 01 Oct 2014 08:38:42 -0700 (PDT) Received: from localhost.localdomain (static-74-96-105-49.washdc.fios.verizon.net. [74.96.105.49]) by mx.google.com with ESMTPSA id e64sm892521qga.34.2014.10.01.08.38.42 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 01 Oct 2014 08:38:42 -0700 (PDT) From: Alex Deucher X-Google-Original-From: Alex Deucher To: dri-devel@lists.freedesktop.org Subject: [PATCH 15/22] drm/radeon: add new callback for info ioctl register accessor Date: Wed, 1 Oct 2014 11:38:20 -0400 Message-Id: <1412177907-24601-16-git-send-email-alexander.deucher@amd.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1412177907-24601-1-git-send-email-alexander.deucher@amd.com> References: <1412177907-24601-1-git-send-email-alexander.deucher@amd.com> Cc: Alex Deucher X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This adds a callback for each asic family to determine what registers are allowed to be read back via the info ioctl. The idea here is to allow usermode to query things like GPU status registers or GPU harvest registers for profiling and determining the gfx config. Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/radeon.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 9e3dc82..7671e01 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -1812,6 +1812,8 @@ struct radeon_asic { u32 (*get_xclk)(struct radeon_device *rdev); /* get the gpu clock counter */ uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); + /* get register for info ioctl */ + int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val); /* gart */ struct { void (*tlb_flush)(struct radeon_device *rdev); @@ -2877,6 +2879,7 @@ static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) +#define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v)) #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))