From patchwork Mon Oct 27 09:49:16 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Courbot X-Patchwork-Id: 5158981 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 3A7929F318 for ; Mon, 27 Oct 2014 09:49:40 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 73567202D1 for ; Mon, 27 Oct 2014 09:49:39 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id C0AC3202B8 for ; Mon, 27 Oct 2014 09:49:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D6E6D6E1EB; Mon, 27 Oct 2014 02:49:36 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from hqemgate15.nvidia.com (hqemgate15.nvidia.com [216.228.121.64]) by gabe.freedesktop.org (Postfix) with ESMTP id 9C25E6E1E9; Mon, 27 Oct 2014 02:49:35 -0700 (PDT) Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Mon, 27 Oct 2014 02:49:39 -0700 Received: from hqemhub03.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Mon, 27 Oct 2014 02:48:56 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Mon, 27 Oct 2014 02:48:56 -0700 Received: from percival.nvidia.com (172.20.144.16) by hqemhub03.nvidia.com (172.20.150.15) with Microsoft SMTP Server (TLS) id 8.3.342.0; Mon, 27 Oct 2014 02:49:34 -0700 From: Alexandre Courbot To: Ben Skeggs , David Airlie , David Herrmann , Lucas Stach , Thierry Reding , Maarten Lankhorst Subject: [PATCH v5 1/4] drm: introduce nv_device_is_cpu_coherent() Date: Mon, 27 Oct 2014 18:49:16 +0900 Message-ID: <1414403359-22332-2-git-send-email-acourbot@nvidia.com> X-Mailer: git-send-email 2.1.2 In-Reply-To: <1414403359-22332-1-git-send-email-acourbot@nvidia.com> References: <1414403359-22332-1-git-send-email-acourbot@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Cc: gnurou@gmail.com, nouveau@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add a function allowing us to know whether a device is CPU-coherent, i.e. accesses performed by the CPU on GPU-mapped buffers will be immediately visible on the GPU side and vice-versa. For now, a device is considered to be coherent if it uses the PCI bus on a non-ARM architecture. Signed-off-by: Alexandre Courbot --- lib/core/os.h | 2 ++ nvkm/include/core/device.h | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/lib/core/os.h b/lib/core/os.h index fba9542292ac..79462eb2cfd4 100644 --- a/lib/core/os.h +++ b/lib/core/os.h @@ -101,6 +101,8 @@ typedef dma_addr_t resource_size_t; #define __printf(a,b) #define __user +#define IS_ENABLED(x) (0) + static inline int order_base_2(u64 base) { diff --git a/nvkm/include/core/device.h b/nvkm/include/core/device.h index 1d9d893929bb..0d839e1ddaf4 100644 --- a/nvkm/include/core/device.h +++ b/nvkm/include/core/device.h @@ -158,6 +158,12 @@ nv_device_is_pci(struct nouveau_device *device) return device->pdev != NULL; } +static inline bool +nv_device_is_cpu_coherent(struct nouveau_device *device) +{ + return (!IS_ENABLED(CONFIG_ARM) && nv_device_is_pci(device)); +} + static inline struct device * nv_device_base(struct nouveau_device *device) {