From patchwork Mon Oct 27 14:14:57 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Joe Perches X-Patchwork-Id: 5160991 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 1CC429F43D for ; Mon, 27 Oct 2014 14:15:09 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5A8D72012F for ; Mon, 27 Oct 2014 14:15:08 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 0391C2015E for ; Mon, 27 Oct 2014 14:15:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5F6E46E22C; Mon, 27 Oct 2014 07:15:05 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from smtprelay.hostedemail.com (smtprelay0161.hostedemail.com [216.40.44.161]) by gabe.freedesktop.org (Postfix) with ESMTP id E7CDF6E22C for ; Mon, 27 Oct 2014 07:15:03 -0700 (PDT) Received: from filter.hostedemail.com (ff-bigip1 [10.5.19.254]) by smtprelay06.hostedemail.com (Postfix) with ESMTP id 9DC709EA12; Mon, 27 Oct 2014 14:15:02 +0000 (UTC) X-Session-Marker: 6A6F6540706572636865732E636F6D X-Spam-Summary: 2, 0, 0, , d41d8cd98f00b204, joe@perches.com, :::::::::, RULES_HIT:41:355:379:541:800:960:973:988:989:1260:1277:1311:1313:1314:1345:1359:1373:1437:1515:1516:1518:1534:1541:1593:1594:1711:1730:1747:1777:1792:2393:2559:2562:2828:3138:3139:3140:3141:3142:3352:3865:3866:3867:3868:3871:4321:4605:5007:6261:10004:10400:10848:11026:11232:11473:11657:11658:11914:12043:12296:12438:12517:12519:12555:13069:13311:13357:14096:14097:14394:21080, 0, RBL:none, CacheIP:none, Bayesian:0.5, 0.5, 0.5, Netcheck:none, DomainCache:0, MSF:not bulk, SPF:fn, MSBL:0, DNSBL:none, Custom_rules:0:0:0 X-HE-Tag: baby26_2bd63b918ed27 X-Filterd-Recvd-Size: 2179 Received: from joe-X200MA.home (pool-71-103-235-196.lsanca.fios.verizon.net [71.103.235.196]) (Authenticated sender: joe@perches.com) by omf11.hostedemail.com (Postfix) with ESMTPA; Mon, 27 Oct 2014 14:15:01 +0000 (UTC) Message-ID: <1414419297.8884.5.camel@perches.com> Subject: [PATCH 02/11 V2] radeon: evergreen: Fix probable mask then right shift defect From: Joe Perches To: Michel =?ISO-8859-1?Q?D=E4nzer?= Date: Mon, 27 Oct 2014 07:14:57 -0700 In-Reply-To: <544E0D0E.6080206@daenzer.net> References: <88c64cce88264069e0e1637fc874e699e5b226f6.1414387334.git.joe@perches.com> <544E0D0E.6080206@daenzer.net> X-Mailer: Evolution 3.12.7-0ubuntu1 Mime-Version: 1.0 Cc: Alex Deucher , Christian =?ISO-8859-1?Q?K=F6nig?= , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Precedence of & and >> is not the same and is not left to right. shift has higher precedence and should be done after the mask. Add parentheses around the mask. Use the already #defined values instead of hardcoding. Signed-off-by: Joe Perches Reviewed-by: Michel Dänzer --- > I think this should be NUM_SHADER_ENGINES_SHIFT? (Joe can't type) exactly right, thanks Michel drivers/gpu/drm/radeon/evergreen.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index a31f1ca..a97a685 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -3303,7 +3303,8 @@ static void evergreen_gpu_init(struct radeon_device *rdev) rdev->config.evergreen.tile_config |= ((gb_addr_config & 0x30000000) >> 28) << 12; - num_shader_engines = (gb_addr_config & NUM_SHADER_ENGINES(3) >> 12) + 1; + num_shader_engines = ((gb_addr_config & NUM_SHADER_ENGINES_MASK) + >> NUM_SHADER_ENGINES_SHIFT) + 1; if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) { u32 efuse_straps_4;