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[20/72] gpu: ipu-v3: Move DI waveform counter enable/disable to ipu-di

Message ID 1414796095-10107-21-git-send-email-steve_longerbeam@mentor.com (mailing list archive)
State New, archived
Headers show

Commit Message

Steve Longerbeam Oct. 31, 2014, 10:54 p.m. UTC 
Move the DI waveform counter enable/disable out of
ipu_module_enable()/disable(). This should be carried out
when enabling/disabling the DI pixel clock.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/gpu/ipu-v3/ipu-common.c |   37 +++++++++++++++++++------------------
 drivers/gpu/ipu-v3/ipu-di.c     |   13 ++++++++++++-
 drivers/gpu/ipu-v3/ipu-prv.h    |    1 +
 3 files changed, 32 insertions(+), 19 deletions(-)
diff mbox

Patch

diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c
index d3af206..5004f71 100644
--- a/drivers/gpu/ipu-v3/ipu-common.c
+++ b/drivers/gpu/ipu-v3/ipu-common.c
@@ -59,6 +59,25 @@  void ipu_srm_dp_sync_update(struct ipu_soc *ipu)
 }
 EXPORT_SYMBOL_GPL(ipu_srm_dp_sync_update);
 
+void ipu_enable_di_counter(struct ipu_soc *ipu, int di, bool enable)
+{
+	unsigned long flags;
+	u32 val, mask;
+
+	mask = di ? IPU_DI1_COUNTER_RELEASE : IPU_DI0_COUNTER_RELEASE;
+
+	spin_lock_irqsave(&ipu->lock, flags);
+
+	val = ipu_cm_read(ipu, IPU_DISP_GEN);
+	if (enable)
+		val |= mask;
+	else
+		val &= ~mask;
+	ipu_cm_write(ipu, val, IPU_DISP_GEN);
+
+	spin_unlock_irqrestore(&ipu->lock, flags);
+}
+
 enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc)
 {
 	switch (drm_fourcc) {
@@ -407,15 +426,6 @@  int ipu_module_enable(struct ipu_soc *ipu, u32 mask)
 
 	spin_lock_irqsave(&ipu->lock, lock_flags);
 
-	val = ipu_cm_read(ipu, IPU_DISP_GEN);
-
-	if (mask & IPU_CONF_DI0_EN)
-		val |= IPU_DI0_COUNTER_RELEASE;
-	if (mask & IPU_CONF_DI1_EN)
-		val |= IPU_DI1_COUNTER_RELEASE;
-
-	ipu_cm_write(ipu, val, IPU_DISP_GEN);
-
 	val = ipu_cm_read(ipu, IPU_CONF);
 	val |= mask;
 	ipu_cm_write(ipu, val, IPU_CONF);
@@ -437,15 +447,6 @@  int ipu_module_disable(struct ipu_soc *ipu, u32 mask)
 	val &= ~mask;
 	ipu_cm_write(ipu, val, IPU_CONF);
 
-	val = ipu_cm_read(ipu, IPU_DISP_GEN);
-
-	if (mask & IPU_CONF_DI0_EN)
-		val &= ~IPU_DI0_COUNTER_RELEASE;
-	if (mask & IPU_CONF_DI1_EN)
-		val &= ~IPU_DI1_COUNTER_RELEASE;
-
-	ipu_cm_write(ipu, val, IPU_DISP_GEN);
-
 	spin_unlock_irqrestore(&ipu->lock, lock_flags);
 
 	return 0;
diff --git a/drivers/gpu/ipu-v3/ipu-di.c b/drivers/gpu/ipu-v3/ipu-di.c
index 7ab19a3..5686969 100644
--- a/drivers/gpu/ipu-v3/ipu-di.c
+++ b/drivers/gpu/ipu-v3/ipu-di.c
@@ -670,7 +670,16 @@  EXPORT_SYMBOL_GPL(ipu_di_enable);
 
 int ipu_di_enable_clock(struct ipu_di *di)
 {
-	return clk_prepare_enable(di->clk_di_pixel);
+	int ret;
+
+	ret = clk_prepare_enable(di->clk_di_pixel);
+	if (ret)
+		return ret;
+
+	ipu_enable_di_counter(di->ipu, di->id, true);
+
+	return 0;
+
 }
 EXPORT_SYMBOL_GPL(ipu_di_enable_clock);
 
@@ -687,6 +696,8 @@  EXPORT_SYMBOL_GPL(ipu_di_disable);
 
 int ipu_di_disable_clock(struct ipu_di *di)
 {
+	ipu_enable_di_counter(di->ipu, di->id, false);
+
 	clk_disable_unprepare(di->clk_di_pixel);
 
 	return 0;
diff --git a/drivers/gpu/ipu-v3/ipu-prv.h b/drivers/gpu/ipu-v3/ipu-prv.h
index bfb1e8a..7797894 100644
--- a/drivers/gpu/ipu-v3/ipu-prv.h
+++ b/drivers/gpu/ipu-v3/ipu-prv.h
@@ -184,6 +184,7 @@  static inline void ipu_idmac_write(struct ipu_soc *ipu, u32 value,
 }
 
 void ipu_srm_dp_sync_update(struct ipu_soc *ipu);
+void ipu_enable_di_counter(struct ipu_soc *ipu, int di, bool enable);
 
 int ipu_module_enable(struct ipu_soc *ipu, u32 mask);
 int ipu_module_disable(struct ipu_soc *ipu, u32 mask);