From patchwork Fri Oct 31 22:54:03 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steve Longerbeam X-Patchwork-Id: 5207501 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 2A6E6C11AC for ; Fri, 31 Oct 2014 23:57:07 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5167D201C0 for ; Fri, 31 Oct 2014 23:57:06 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 616AF20173 for ; Fri, 31 Oct 2014 23:57:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 66F596E86D; Fri, 31 Oct 2014 16:56:40 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-pa0-f54.google.com (mail-pa0-f54.google.com [209.85.220.54]) by gabe.freedesktop.org (Postfix) with ESMTP id EC3406E851 for ; Fri, 31 Oct 2014 15:57:04 -0700 (PDT) Received: by mail-pa0-f54.google.com with SMTP id rd3so8528088pab.41 for ; Fri, 31 Oct 2014 15:57:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3UAj/nErkIIvrLgS4L0I0RBRry+ZNXYuapYX4EIctko=; b=e1APwjnWQKPtKuEB6Fiy0ZV6YOC0LbcFmpDjmsjA0qxJuww3SJ6TsVmOlF8nWEPKws Rj8nA8H4j6dKRorDPg6oSKgDO4gf7/eHbh00SGhH6C8t+mYasrQJ9YPTO/fWbhfWgsRt Xatn4yswO/HD4WlJHu3sGztVvvG4dqYF8vEKEOHp0CLRDU7mxqtbIsuWrj7PTVCtlrH4 9fOYaVxM/9C+F4VxCYjBV+6YfO5wR8IsS6cTOtnG6nqjxxubAVbIxa8wI8wKANJVHhdi efjQlPTOCSi7Q2LOLXs4LUa+iVrin33O6dv/O7I1hptycL8FPdq/EQiTT3TqPLBnVNFz 6Fkw== X-Received: by 10.66.235.36 with SMTP id uj4mr5097000pac.103.1414796224844; Fri, 31 Oct 2014 15:57:04 -0700 (PDT) Received: from mothership.mgc.mentorg.com (c-50-152-159-227.hsd1.ca.comcast.net. [50.152.159.227]) by mx.google.com with ESMTPSA id ev8sm10870656pdb.28.2014.10.31.15.57.03 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 31 Oct 2014 15:57:04 -0700 (PDT) From: Steve Longerbeam X-Google-Original-From: Steve Longerbeam To: dri-devel@lists.freedesktop.org Subject: [PATCH 20/72] gpu: ipu-v3: Move DI waveform counter enable/disable to ipu-di Date: Fri, 31 Oct 2014 15:54:03 -0700 Message-Id: <1414796095-10107-21-git-send-email-steve_longerbeam@mentor.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1414796095-10107-1-git-send-email-steve_longerbeam@mentor.com> References: <1414796095-10107-1-git-send-email-steve_longerbeam@mentor.com> X-Mailman-Approved-At: Fri, 31 Oct 2014 16:56:31 -0700 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Move the DI waveform counter enable/disable out of ipu_module_enable()/disable(). This should be carried out when enabling/disabling the DI pixel clock. Signed-off-by: Steve Longerbeam --- drivers/gpu/ipu-v3/ipu-common.c | 37 +++++++++++++++++++------------------ drivers/gpu/ipu-v3/ipu-di.c | 13 ++++++++++++- drivers/gpu/ipu-v3/ipu-prv.h | 1 + 3 files changed, 32 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c index d3af206..5004f71 100644 --- a/drivers/gpu/ipu-v3/ipu-common.c +++ b/drivers/gpu/ipu-v3/ipu-common.c @@ -59,6 +59,25 @@ void ipu_srm_dp_sync_update(struct ipu_soc *ipu) } EXPORT_SYMBOL_GPL(ipu_srm_dp_sync_update); +void ipu_enable_di_counter(struct ipu_soc *ipu, int di, bool enable) +{ + unsigned long flags; + u32 val, mask; + + mask = di ? IPU_DI1_COUNTER_RELEASE : IPU_DI0_COUNTER_RELEASE; + + spin_lock_irqsave(&ipu->lock, flags); + + val = ipu_cm_read(ipu, IPU_DISP_GEN); + if (enable) + val |= mask; + else + val &= ~mask; + ipu_cm_write(ipu, val, IPU_DISP_GEN); + + spin_unlock_irqrestore(&ipu->lock, flags); +} + enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc) { switch (drm_fourcc) { @@ -407,15 +426,6 @@ int ipu_module_enable(struct ipu_soc *ipu, u32 mask) spin_lock_irqsave(&ipu->lock, lock_flags); - val = ipu_cm_read(ipu, IPU_DISP_GEN); - - if (mask & IPU_CONF_DI0_EN) - val |= IPU_DI0_COUNTER_RELEASE; - if (mask & IPU_CONF_DI1_EN) - val |= IPU_DI1_COUNTER_RELEASE; - - ipu_cm_write(ipu, val, IPU_DISP_GEN); - val = ipu_cm_read(ipu, IPU_CONF); val |= mask; ipu_cm_write(ipu, val, IPU_CONF); @@ -437,15 +447,6 @@ int ipu_module_disable(struct ipu_soc *ipu, u32 mask) val &= ~mask; ipu_cm_write(ipu, val, IPU_CONF); - val = ipu_cm_read(ipu, IPU_DISP_GEN); - - if (mask & IPU_CONF_DI0_EN) - val &= ~IPU_DI0_COUNTER_RELEASE; - if (mask & IPU_CONF_DI1_EN) - val &= ~IPU_DI1_COUNTER_RELEASE; - - ipu_cm_write(ipu, val, IPU_DISP_GEN); - spin_unlock_irqrestore(&ipu->lock, lock_flags); return 0; diff --git a/drivers/gpu/ipu-v3/ipu-di.c b/drivers/gpu/ipu-v3/ipu-di.c index 7ab19a3..5686969 100644 --- a/drivers/gpu/ipu-v3/ipu-di.c +++ b/drivers/gpu/ipu-v3/ipu-di.c @@ -670,7 +670,16 @@ EXPORT_SYMBOL_GPL(ipu_di_enable); int ipu_di_enable_clock(struct ipu_di *di) { - return clk_prepare_enable(di->clk_di_pixel); + int ret; + + ret = clk_prepare_enable(di->clk_di_pixel); + if (ret) + return ret; + + ipu_enable_di_counter(di->ipu, di->id, true); + + return 0; + } EXPORT_SYMBOL_GPL(ipu_di_enable_clock); @@ -687,6 +696,8 @@ EXPORT_SYMBOL_GPL(ipu_di_disable); int ipu_di_disable_clock(struct ipu_di *di) { + ipu_enable_di_counter(di->ipu, di->id, false); + clk_disable_unprepare(di->clk_di_pixel); return 0; diff --git a/drivers/gpu/ipu-v3/ipu-prv.h b/drivers/gpu/ipu-v3/ipu-prv.h index bfb1e8a..7797894 100644 --- a/drivers/gpu/ipu-v3/ipu-prv.h +++ b/drivers/gpu/ipu-v3/ipu-prv.h @@ -184,6 +184,7 @@ static inline void ipu_idmac_write(struct ipu_soc *ipu, u32 value, } void ipu_srm_dp_sync_update(struct ipu_soc *ipu); +void ipu_enable_di_counter(struct ipu_soc *ipu, int di, bool enable); int ipu_module_enable(struct ipu_soc *ipu, u32 mask); int ipu_module_disable(struct ipu_soc *ipu, u32 mask);