From patchwork Fri Oct 31 22:54:12 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steve Longerbeam X-Patchwork-Id: 5207651 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 7A94FC11AD for ; Fri, 31 Oct 2014 23:57:21 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7788520172 for ; Fri, 31 Oct 2014 23:57:19 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 15593201C0 for ; Fri, 31 Oct 2014 23:57:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C86076E886; Fri, 31 Oct 2014 16:56:41 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-pa0-f43.google.com (mail-pa0-f43.google.com [209.85.220.43]) by gabe.freedesktop.org (Postfix) with ESMTP id 777DB6E849 for ; Fri, 31 Oct 2014 15:57:12 -0700 (PDT) Received: by mail-pa0-f43.google.com with SMTP id eu11so8580466pac.16 for ; Fri, 31 Oct 2014 15:57:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4NZY/8CvuAjPCshFFv4ungM1IjN2ESv2V9hfocDqO3w=; b=upT2gjlzRzR3FPhNk+qRQi67dMePs+DlrO9yiQYL8u9SD3AM5nG/jvh/I0giL2CZnC Ead3o6XKsVGfvRfjhyLb00UP+qQ57DJEok1oMT4UGpP+AQl/isKJagyvsaWGwFw4xxby 7Do/K04CWiAZtrMtL1lzfiGqLfT5hjjbiSYXemm8wQGXT8uNta6fo7YThRfb5rmPolK5 P0I6q5nhp1BLvc9C/4aIS8E22Y1B7LAfxN+OJMly5opqbR6cf9UcAa1IY5HfFNgpUnAn 8uHI/vMDhehnwE0wO/WMGxL7XT5CxMFPCaxWZZrnwY3T4t7QH4BcskQs9H5FxCl4Idtt 9/mQ== X-Received: by 10.68.57.140 with SMTP id i12mr19534839pbq.115.1414796232267; Fri, 31 Oct 2014 15:57:12 -0700 (PDT) Received: from mothership.mgc.mentorg.com (c-50-152-159-227.hsd1.ca.comcast.net. [50.152.159.227]) by mx.google.com with ESMTPSA id ev8sm10870656pdb.28.2014.10.31.15.57.11 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 31 Oct 2014 15:57:11 -0700 (PDT) From: Steve Longerbeam X-Google-Original-From: Steve Longerbeam To: dri-devel@lists.freedesktop.org Subject: [PATCH 29/72] gpu: ipu-v3: Change signal names in struct ipu_di_signal_cfg Date: Fri, 31 Oct 2014 15:54:12 -0700 Message-Id: <1414796095-10107-30-git-send-email-steve_longerbeam@mentor.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1414796095-10107-1-git-send-email-steve_longerbeam@mentor.com> References: <1414796095-10107-1-git-send-email-steve_longerbeam@mentor.com> X-Mailman-Approved-At: Fri, 31 Oct 2014 16:56:31 -0700 Cc: Deepak Das X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch changes signal names in struct ipu_di_signal_cfg as per the industry standard names, and renames fields that were using CamelCase. Signed-off-by: Deepak Das Signed-off-by: Steve Longerbeam --- drivers/gpu/ipu-v3/ipu-di.c | 68 +++++++++++++++++----------------- drivers/staging/imx-drm/ipuv3-crtc.c | 16 ++++---- include/video/imx-ipu-v3.h | 16 ++++---- 3 files changed, 50 insertions(+), 50 deletions(-) diff --git a/drivers/gpu/ipu-v3/ipu-di.c b/drivers/gpu/ipu-v3/ipu-di.c index 47615ce..b306f07 100644 --- a/drivers/gpu/ipu-v3/ipu-di.c +++ b/drivers/gpu/ipu-v3/ipu-di.c @@ -207,10 +207,10 @@ static void ipu_di_sync_config(struct ipu_di *di, struct di_sync_config *config, static void ipu_di_sync_config_interlaced(struct ipu_di *di, struct ipu_di_signal_cfg *sig) { - u32 h_total = sig->width + sig->h_sync_width + - sig->h_start_width + sig->h_end_width; - u32 v_total = sig->height + sig->v_sync_width + - sig->v_start_width + sig->v_end_width; + u32 h_total = sig->width + sig->h_sync_len + + sig->h_back_porch + sig->h_front_porch; + u32 v_total = sig->height + sig->v_sync_len + + sig->v_back_porch + sig->v_front_porch; u32 reg; struct di_sync_config cfg[] = { { @@ -229,7 +229,7 @@ static void ipu_di_sync_config_interlaced(struct ipu_di *di, }, { .run_count = v_total / 2 - 1, .run_src = DI_SYNC_HSYNC, - .offset_count = sig->v_start_width, + .offset_count = sig->v_back_porch, .offset_src = DI_SYNC_HSYNC, .repeat_count = 2, .cnt_clr_src = DI_SYNC_VSYNC, @@ -249,7 +249,7 @@ static void ipu_di_sync_config_interlaced(struct ipu_di *di, .cnt_clr_src = DI_SYNC_VSYNC, }, { .run_src = DI_SYNC_CLK, - .offset_count = sig->h_start_width, + .offset_count = sig->h_back_porch, .offset_src = DI_SYNC_CLK, .repeat_count = sig->width, .cnt_clr_src = 5, @@ -277,10 +277,10 @@ static void ipu_di_sync_config_interlaced(struct ipu_di *di, static void ipu_di_sync_config_noninterlaced(struct ipu_di *di, struct ipu_di_signal_cfg *sig, int div) { - u32 h_total = sig->width + sig->h_sync_width + sig->h_start_width + - sig->h_end_width; - u32 v_total = sig->height + sig->v_sync_width + sig->v_start_width + - sig->v_end_width; + u32 h_total = sig->width + sig->h_sync_len + sig->h_back_porch + + sig->h_front_porch; + u32 v_total = sig->height + sig->v_sync_len + sig->v_back_porch + + sig->v_front_porch; struct di_sync_config cfg[] = { { /* 1: INT_HSYNC */ @@ -294,25 +294,25 @@ static void ipu_di_sync_config_noninterlaced(struct ipu_di *di, .offset_src = DI_SYNC_CLK, .cnt_polarity_gen_en = 1, .cnt_polarity_trigger_src = DI_SYNC_CLK, - .cnt_down = sig->h_sync_width * 2, + .cnt_down = sig->h_sync_len * 2, } , { /* PIN3: VSYNC */ .run_count = v_total - 1, .run_src = DI_SYNC_INT_HSYNC, .cnt_polarity_gen_en = 1, .cnt_polarity_trigger_src = DI_SYNC_INT_HSYNC, - .cnt_down = sig->v_sync_width * 2, + .cnt_down = sig->v_sync_len * 2, } , { /* 4: Line Active */ .run_src = DI_SYNC_HSYNC, - .offset_count = sig->v_sync_width + sig->v_start_width, + .offset_count = sig->v_sync_len + sig->v_back_porch, .offset_src = DI_SYNC_HSYNC, .repeat_count = sig->height, .cnt_clr_src = DI_SYNC_VSYNC, } , { /* 5: Pixel Active, referenced by DC */ .run_src = DI_SYNC_CLK, - .offset_count = sig->h_sync_width + sig->h_start_width, + .offset_count = sig->h_sync_len + sig->h_back_porch, .offset_src = DI_SYNC_CLK, .repeat_count = sig->width, .cnt_clr_src = 5, /* Line Active */ @@ -339,7 +339,7 @@ static void ipu_di_sync_config_noninterlaced(struct ipu_di *di, } , { /* 3: Line Active */ .run_src = DI_SYNC_INT_HSYNC, - .offset_count = sig->v_sync_width + sig->v_start_width, + .offset_count = sig->v_sync_len + sig->v_back_porch, .offset_src = DI_SYNC_INT_HSYNC, .repeat_count = sig->height, .cnt_clr_src = 3 /* VSYNC */, @@ -351,11 +351,11 @@ static void ipu_di_sync_config_noninterlaced(struct ipu_di *di, .offset_src = DI_SYNC_CLK, .cnt_polarity_gen_en = 1, .cnt_polarity_trigger_src = DI_SYNC_CLK, - .cnt_down = sig->h_sync_width * 2, + .cnt_down = sig->h_sync_len * 2, } , { /* 5: Pixel Active signal to DC */ .run_src = DI_SYNC_CLK, - .offset_count = sig->h_sync_width + sig->h_start_width, + .offset_count = sig->h_sync_len + sig->h_back_porch, .offset_src = DI_SYNC_CLK, .repeat_count = sig->width, .cnt_clr_src = 4, /* Line Active */ @@ -367,7 +367,7 @@ static void ipu_di_sync_config_noninterlaced(struct ipu_di *di, .offset_src = DI_SYNC_INT_HSYNC, .cnt_polarity_gen_en = 1, .cnt_polarity_trigger_src = DI_SYNC_INT_HSYNC, - .cnt_down = sig->v_sync_width * 2, + .cnt_down = sig->v_sync_len * 2, } , { /* PIN4: HSYNC for VGA via TVEv2 on i.MX53-QSB */ .run_count = h_total - 1, @@ -376,7 +376,7 @@ static void ipu_di_sync_config_noninterlaced(struct ipu_di *di, .offset_src = DI_SYNC_CLK, .cnt_polarity_gen_en = 1, .cnt_polarity_trigger_src = DI_SYNC_CLK, - .cnt_down = sig->h_sync_width * 2, + .cnt_down = sig->h_sync_len * 2, } , { /* PIN6: VSYNC for VGA via TVEv2 on i.MX53-QSB */ .run_count = v_total - 1, @@ -385,7 +385,7 @@ static void ipu_di_sync_config_noninterlaced(struct ipu_di *di, .offset_src = DI_SYNC_INT_HSYNC, .cnt_polarity_gen_en = 1, .cnt_polarity_trigger_src = DI_SYNC_INT_HSYNC, - .cnt_down = sig->v_sync_width * 2, + .cnt_down = sig->v_sync_len * 2, } , { /* unused */ }, @@ -522,15 +522,15 @@ static void ipu_di_config_clock(struct ipu_di *di, static void adapt_panel_to_ipu_restricitions(struct ipu_di *di, struct ipu_di_signal_cfg *sig) { - if (sig->v_end_width < 2) { - uint16_t diff = 2 - sig->v_end_width; - - if (sig->v_start_width >= diff) { - sig->v_end_width = 2; - sig->v_start_width -= diff; - } else if (sig->v_sync_width > diff) { - sig->v_end_width = 2; - sig->v_sync_width = sig->v_sync_width - diff; + if (sig->v_front_porch < 2) { + uint16_t diff = 2 - sig->v_front_porch; + + if (sig->v_back_porch >= diff) { + sig->v_front_porch = 2; + sig->v_back_porch -= diff; + } else if (sig->v_sync_len > diff) { + sig->v_front_porch = 2; + sig->v_sync_len = sig->v_sync_len - diff; } else dev_warn(di->ipu->dev, "di%d: failed to adapt timing\n", di->id); @@ -550,7 +550,7 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig) dev_dbg(di->ipu->dev, "di%d: panel size = %d x %d\n", di->id, sig->width, sig->height); - if ((sig->v_sync_width == 0) || (sig->h_sync_width == 0)) + if ((sig->v_sync_len == 0) || (sig->h_sync_len == 0)) return -EINVAL; adapt_panel_to_ipu_restricitions(di, sig); @@ -589,9 +589,9 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig) vsync_cnt = 7; - if (sig->Hsync_pol) + if (sig->hsync_pol) di_gen |= DI_GEN_POLARITY_3; - if (sig->Vsync_pol) + if (sig->vsync_pol) di_gen |= DI_GEN_POLARITY_2; } else { ipu_di_sync_config_noninterlaced(di, sig, div); @@ -605,7 +605,7 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig) if (!(sig->hsync_pin == 2 && sig->vsync_pin == 3)) vsync_cnt = 6; - if (sig->Hsync_pol) { + if (sig->hsync_pol) { if (sig->hsync_pin == 2) di_gen |= DI_GEN_POLARITY_2; else if (sig->hsync_pin == 4) @@ -613,7 +613,7 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig) else if (sig->hsync_pin == 7) di_gen |= DI_GEN_POLARITY_7; } - if (sig->Vsync_pol) { + if (sig->vsync_pol) { if (sig->vsync_pin == 3) di_gen |= DI_GEN_POLARITY_3; else if (sig->vsync_pin == 6) diff --git a/drivers/staging/imx-drm/ipuv3-crtc.c b/drivers/staging/imx-drm/ipuv3-crtc.c index be24cb9..8b4440a 100644 --- a/drivers/staging/imx-drm/ipuv3-crtc.c +++ b/drivers/staging/imx-drm/ipuv3-crtc.c @@ -159,22 +159,22 @@ static int ipu_crtc_mode_set(struct drm_crtc *crtc, if (mode->flags & DRM_MODE_FLAG_INTERLACE) sig_cfg.interlaced = 1; if (mode->flags & DRM_MODE_FLAG_PHSYNC) - sig_cfg.Hsync_pol = 1; + sig_cfg.hsync_pol = 1; if (mode->flags & DRM_MODE_FLAG_PVSYNC) - sig_cfg.Vsync_pol = 1; + sig_cfg.vsync_pol = 1; sig_cfg.enable_pol = 1; sig_cfg.clk_pol = 0; sig_cfg.width = mode->hdisplay; sig_cfg.height = mode->vdisplay; sig_cfg.pixel_fmt = out_pixel_fmt; - sig_cfg.h_start_width = mode->htotal - mode->hsync_end; - sig_cfg.h_sync_width = mode->hsync_end - mode->hsync_start; - sig_cfg.h_end_width = mode->hsync_start - mode->hdisplay; + sig_cfg.h_back_porch = mode->htotal - mode->hsync_end; + sig_cfg.h_sync_len = mode->hsync_end - mode->hsync_start; + sig_cfg.h_front_porch = mode->hsync_start - mode->hdisplay; - sig_cfg.v_start_width = mode->vtotal - mode->vsync_end; - sig_cfg.v_sync_width = mode->vsync_end - mode->vsync_start; - sig_cfg.v_end_width = mode->vsync_start - mode->vdisplay; + sig_cfg.v_back_porch = mode->vtotal - mode->vsync_end; + sig_cfg.v_sync_len = mode->vsync_end - mode->vsync_start; + sig_cfg.v_front_porch = mode->vsync_start - mode->vdisplay; sig_cfg.pixelclock = mode->clock * 1000; sig_cfg.clkflags = ipu_crtc->di_clkflags; diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h index d2f621d..7e1bc61 100644 --- a/include/video/imx-ipu-v3.h +++ b/include/video/imx-ipu-v3.h @@ -40,18 +40,18 @@ struct ipu_di_signal_cfg { unsigned data_pol:1; /* true = inverted */ unsigned clk_pol:1; /* true = rising edge */ unsigned enable_pol:1; - unsigned Hsync_pol:1; /* true = active high */ - unsigned Vsync_pol:1; + unsigned hsync_pol:1; /* true = active high */ + unsigned vsync_pol:1; u16 width; u16 height; u32 pixel_fmt; - u16 h_start_width; - u16 h_sync_width; - u16 h_end_width; - u16 v_start_width; - u16 v_sync_width; - u16 v_end_width; + u16 h_back_porch; + u16 h_sync_len; + u16 h_front_porch; + u16 v_back_porch; + u16 v_sync_len; + u16 v_front_porch; u32 v_to_h_sync; unsigned long pixelclock; #define IPU_DI_CLKMODE_SYNC (1 << 0)