| Message ID | 1414796095-10107-6-git-send-email-steve_longerbeam@mentor.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Am Freitag, den 31.10.2014, 15:53 -0700 schrieb Steve Longerbeam: > Select pll3_usb_otg for ldb_di clock for rev 1.0 chips. > > Signed-off-by: Jiada Wang <jiada_wang@mentor.com> > Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> > --- > arch/arm/mach-imx/clk-imx6q.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c > index 86b58fc..68064a6 100644 > --- a/arch/arm/mach-imx/clk-imx6q.c > +++ b/arch/arm/mach-imx/clk-imx6q.c > @@ -481,6 +481,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) > cpu_is_imx6dl()) { > clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); > clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); > + } else { > + clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL3_USB_OTG]); > + clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL3_USB_OTG]); > } > > clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL2_PFD0_352M]); Does the issue with the LDB DI mux glitch locking up the LDB DI divider also affect rev 1.0 silicon? (http://lists.infradead.org/pipermail/linux-arm-kernel/2014-July/268864.html) We probably shouldn't touch LDB_DIx_SEL here for the other revisions either. In any case, this would be a patch for the linux-arm-kernel mailing list. regards Philipp
On 11/03/2014 04:30 AM, Philipp Zabel wrote: > Am Freitag, den 31.10.2014, 15:53 -0700 schrieb Steve Longerbeam: >> Select pll3_usb_otg for ldb_di clock for rev 1.0 chips. >> >> Signed-off-by: Jiada Wang <jiada_wang@mentor.com> >> Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> >> --- >> arch/arm/mach-imx/clk-imx6q.c | 3 +++ >> 1 file changed, 3 insertions(+) >> >> diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c >> index 86b58fc..68064a6 100644 >> --- a/arch/arm/mach-imx/clk-imx6q.c >> +++ b/arch/arm/mach-imx/clk-imx6q.c >> @@ -481,6 +481,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) >> cpu_is_imx6dl()) { >> clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); >> clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); >> + } else { >> + clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL3_USB_OTG]); >> + clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL3_USB_OTG]); >> } >> >> clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL2_PFD0_352M]); > Does the issue with the LDB DI mux glitch locking up the LDB DI divider > also affect rev 1.0 silicon? > (http://lists.infradead.org/pipermail/linux-arm-kernel/2014-July/268864.html) I can't say for sure, but I would guess that it does. Internally we are using Freescale's workaround patch for this problem, but it has a lot of issues, most of which is that it needs to be incorporated into the clk API so that the workaround would be applied whenever the LDB parent mux is changed. Steve
On Mon, Nov 3, 2014 at 5:17 PM, Steve Longerbeam <steve_longerbeam@mentor.com> wrote: > Internally we are using Freescale's workaround patch for this problem, > but it has a lot of issues, most of which is that it needs to be incorporated > into the clk API so that the workaround would be applied whenever the > LDB parent mux is changed. Could you please post a patch with this approach? It would be really nice to have this fixed in mainline.
On 11/03/2014 12:06 PM, Fabio Estevam wrote: > On Mon, Nov 3, 2014 at 5:17 PM, Steve Longerbeam > <steve_longerbeam@mentor.com> wrote: > >> Internally we are using Freescale's workaround patch for this problem, >> but it has a lot of issues, most of which is that it needs to be incorporated >> into the clk API so that the workaround would be applied whenever the >> LDB parent mux is changed. > Could you please post a patch with this approach? It would be really > nice to have this fixed in mainline. Hmm, well I reviewed the Freescale patch again, and it won't be so simple. The patch assumes the ldb_di_clk_sel mux is set to the reset default mmdc_ch1_axi source, and that's a central premise of the whole patch. When the workaround is folded into the clk set_parent ops, this assumption can't be made any more. I'm not sure I can capably generalize this patch to switch away from any of the mux sources to any other, avoiding glitch generation, given that there appears to be so many undocumented pieces in the CCM module. Is there someone at Freescale who can take this on? Steve
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 86b58fc..68064a6 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -481,6 +481,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) cpu_is_imx6dl()) { clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); + } else { + clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL3_USB_OTG]); + clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL3_USB_OTG]); } clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL2_PFD0_352M]);