From patchwork Fri Oct 31 22:54:42 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steve Longerbeam X-Patchwork-Id: 5207351 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id D33C0C11AD for ; Fri, 31 Oct 2014 23:56:53 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E2FE52014A for ; Fri, 31 Oct 2014 23:56:52 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id EBD1420120 for ; Fri, 31 Oct 2014 23:56:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 296F06E854; Fri, 31 Oct 2014 16:56:39 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-pd0-f171.google.com (mail-pd0-f171.google.com [209.85.192.171]) by gabe.freedesktop.org (Postfix) with ESMTP id 3C5596E855 for ; Fri, 31 Oct 2014 15:57:37 -0700 (PDT) Received: by mail-pd0-f171.google.com with SMTP id r10so8098989pdi.30 for ; Fri, 31 Oct 2014 15:57:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kC5CP8iBiAcILBB+ygXW+TS3HF8TMjL2PSM0HodNWRE=; b=NMsQX+7lsJEGBtffnMb1ardws8NsU1n95ZBqlinZNoS61BI9+hno2nqPxv9RJc5brA x/G2n+I7Z9zru9vgSTNR7NiRd+JdooDgn2cgHdpMSWbnRW11iebU7tQ4Fz/Fl7CjQVxP kkQoRTPTl1pwSiK+zDsWH8zQZnPFycT+r6tkLSpH6UAT4n+wb3r9h+nhZ6WuieG+sk4+ fNSHfFyGHPKdKl0c3r1oTcLsZwpZKjLwEqGjoqqlQEsOjaiTGgOz7CDEBDYIR9kzbEX9 dxJBmM5u19iAKIt5JdF7jdgAxQ0Qbl4TepSyPTsGiAKVZ+jdDU0TwbWiRnUYUdVcJ3WR IsQw== X-Received: by 10.68.93.132 with SMTP id cu4mr27786433pbb.36.1414796257118; Fri, 31 Oct 2014 15:57:37 -0700 (PDT) Received: from mothership.mgc.mentorg.com (c-50-152-159-227.hsd1.ca.comcast.net. [50.152.159.227]) by mx.google.com with ESMTPSA id ev8sm10870656pdb.28.2014.10.31.15.57.36 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 31 Oct 2014 15:57:36 -0700 (PDT) From: Steve Longerbeam X-Google-Original-From: Steve Longerbeam To: dri-devel@lists.freedesktop.org Subject: [PATCH 59/72] imx-drm: hdmi: set DI clock source to DI pre clock Date: Fri, 31 Oct 2014 15:54:42 -0700 Message-Id: <1414796095-10107-60-git-send-email-steve_longerbeam@mentor.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1414796095-10107-1-git-send-email-steve_longerbeam@mentor.com> References: <1414796095-10107-1-git-send-email-steve_longerbeam@mentor.com> X-Mailman-Approved-At: Fri, 31 Oct 2014 16:56:32 -0700 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP If DI is firstly bound to ldb and then re-bound to HDMI, DI clock source will still be routed to LDB clock by ldb driver. In HDMI driver's encoder_prepare, we have to set DI clock source to the parent di_pre clock mux to ensure we are having correct clock chain to drive HDMI display. Signed-off-by: Steve Longerbeam Signed-off-by: Jiada Wang --- arch/arm/boot/dts/imx6dl.dtsi | 8 ++++++++ arch/arm/boot/dts/imx6q.dtsi | 12 ++++++++++++ arch/arm/boot/dts/imx6qdl.dtsi | 3 --- drivers/staging/imx-drm/imx-hdmi.c | 32 +++++++++++++++++++++++++++++++- 4 files changed, 51 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index 05af0f4..7d1a1bf 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -104,6 +104,14 @@ &hdmi { compatible = "fsl,imx6dl-hdmi"; + clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>, <&clks IMX6QDL_CLK_HDMI_ISFR>, + <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>, + <&clks IMX6QDL_CLK_IPU1_DI1_PRE_SEL>, + <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, + <&clks IMX6QDL_CLK_IPU1_DI1_SEL>; + clock-names = "iahb", "isfr", + "di0_pre_sel", "di1_pre_sel", + "di0_sel", "di1_sel"; }; &ldb { diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 9d1f88c..7d0a7bc 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -235,6 +235,18 @@ &hdmi { compatible = "fsl,imx6q-hdmi"; + clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>, <&clks IMX6QDL_CLK_HDMI_ISFR>, + <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>, + <&clks IMX6QDL_CLK_IPU1_DI1_PRE_SEL>, + <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>, + <&clks IMX6QDL_CLK_IPU2_DI1_PRE_SEL>, + <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, + <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, + <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, + <&clks IMX6QDL_CLK_IPU2_DI1_SEL>; + clock-names = "iahb", "isfr", + "di0_pre_sel", "di1_pre_sel", "di2_pre_sel", "di3_pre_sel", + "di0_sel", "di1_sel", "di2_sel", "di3_sel"; port@2 { reg = <2>; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 13d6b50..4e3a3e8 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -810,9 +810,6 @@ reg = <0x00120000 0x9000>; interrupts = <0 115 0x04>; gpr = <&gpr>; - clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>, - <&clks IMX6QDL_CLK_HDMI_ISFR>; - clock-names = "iahb", "isfr"; status = "disabled"; port@0 { diff --git a/drivers/staging/imx-drm/imx-hdmi.c b/drivers/staging/imx-drm/imx-hdmi.c index 4ef1c0a..d97fa18 100644 --- a/drivers/staging/imx-drm/imx-hdmi.c +++ b/drivers/staging/imx-drm/imx-hdmi.c @@ -118,6 +118,8 @@ struct imx_hdmi { struct device *dev; struct clk *isfr_clk; struct clk *iahb_clk; + struct clk *di_pre_sel[4]; + struct clk *di_sel[4]; struct hdmi_data_info hdmi_data; int vic; @@ -1452,8 +1454,13 @@ static void imx_hdmi_encoder_dpms(struct drm_encoder *encoder, int mode) static void imx_hdmi_encoder_prepare(struct drm_encoder *encoder) { struct imx_hdmi *hdmi = container_of(encoder, struct imx_hdmi, encoder); + int mux = imx_drm_encoder_get_mux_id(hdmi->dev->of_node, encoder); imx_hdmi_poweroff(hdmi); + + /* set DI clock mux to DI pre clock mux */ + clk_set_parent(hdmi->di_sel[mux], hdmi->di_pre_sel[mux]); + imx_drm_panel_format(encoder, V4L2_PIX_FMT_RGB24, NULL); } @@ -1593,7 +1600,7 @@ static int imx_hdmi_bind(struct device *dev, struct device *master, void *data) struct device_node *ddc_node; struct imx_hdmi *hdmi; struct resource *iores; - int ret; + int i, ret; hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); if (!hdmi) @@ -1629,6 +1636,29 @@ static int imx_hdmi_bind(struct device *dev, struct device *master, void *data) if (IS_ERR(hdmi->regmap)) return PTR_ERR(hdmi->regmap); + for (i = 0; i < 4; i++) { + char clkname[16]; + + sprintf(clkname, "di%d_pre_sel", i); + hdmi->di_pre_sel[i] = devm_clk_get(hdmi->dev, clkname); + if (IS_ERR(hdmi->di_pre_sel[i])) { + ret = PTR_ERR(hdmi->di_pre_sel[i]); + hdmi->di_pre_sel[i] = NULL; + break; + } + + sprintf(clkname, "di%d_sel", i); + hdmi->di_sel[i] = devm_clk_get(hdmi->dev, clkname); + if (IS_ERR(hdmi->di_sel[i])) { + ret = PTR_ERR(hdmi->di_sel[i]); + hdmi->di_pre_sel[i] = NULL; + hdmi->di_sel[i] = NULL; + break; + } + } + if (i == 0) + return ret; + hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr"); if (IS_ERR(hdmi->isfr_clk)) { ret = PTR_ERR(hdmi->isfr_clk);