From patchwork Mon Dec 1 20:51:24 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: jilai wang X-Patchwork-Id: 5416341 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 54D069F30B for ; Tue, 2 Dec 2014 01:14:49 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B349620274 for ; Tue, 2 Dec 2014 01:14:45 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id BDBA72028D for ; Tue, 2 Dec 2014 01:14:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E12C96E5D2; Mon, 1 Dec 2014 17:14:25 -0800 (PST) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from smtp.codeaurora.org (smtp.codeaurora.org [198.145.11.231]) by gabe.freedesktop.org (Postfix) with ESMTP id 139CA6E384 for ; Mon, 1 Dec 2014 12:51:32 -0800 (PST) Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id F16CA13FE35; Mon, 1 Dec 2014 20:51:31 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 486) id E17DC13FE62; Mon, 1 Dec 2014 20:51:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from yyzubuntu29.qualcomm.com (rrcs-67-52-130-30.west.biz.rr.com [67.52.130.30]) (using TLSv1.1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: jilaiw@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 892E713FE35; Mon, 1 Dec 2014 20:51:30 +0000 (UTC) From: Jilai Wang To: dri-devel@lists.freedesktop.org Subject: [PATCH 1/2] drm/msm/hdmi: add register description for HDMI HDCP support Date: Mon, 1 Dec 2014 15:51:24 -0500 Message-Id: <1417467084-4579-1-git-send-email-jilaiw@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 X-Virus-Scanned: ClamAV using ClamSMTP X-Mailman-Approved-At: Mon, 01 Dec 2014 17:14:24 -0800 Cc: Jilai Wang , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Add HDCP related register description. Signed-off-by: Jiali Wang --- drivers/gpu/drm/msm/hdmi/hdmi.xml.h | 76 +++++++++++++++++++++++++++++-------- 1 file changed, 60 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h index 76fd0cf..6dd6168 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h +++ b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h @@ -8,16 +8,8 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 647 bytes, from 2013-11-30 14:45:35) -- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20457 bytes, from 2014-08-01 12:22:48) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2014-07-17 15:34:33) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2014-07-17 15:34:33) -- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) -- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) -- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-08-01 12:23:53) -- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12) -- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 23613 bytes, from 2014-07-17 15:33:30) +- /local/mnt2/workspace2/jilaiw/chromeos/envytools/envytools/rnndb/hdmi/hdmi.xml ( 25125 bytes, from 2014-11-24 23:30:39) +- /local/mnt2/workspace2/jilaiw/chromeos/envytools/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2014-11-24 22:27:21) Copyright (C) 2013-2014 by the following authors: - Rob Clark (robclark) @@ -45,12 +37,14 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. enum hdmi_hdcp_key_state { - NO_KEYS = 0, - NOT_CHECKED = 1, - CHECKING = 2, - KEYS_VALID = 3, - AKSV_INVALID = 4, - CHECKSUM_MISMATCH = 5, + HDCP_KEYS_STATE_NO_KEYS = 0, + HDCP_KEYS_STATE_NOT_CHECKED = 1, + HDCP_KEYS_STATE_CHECKING = 2, + HDCP_KEYS_STATE_VALID = 3, + HDCP_KEYS_STATE_AKSV_NOT_VALID = 4, + HDCP_KEYS_STATE_CHKSUM_MISMATCH = 5, + HDCP_KEYS_STATE_PROD_AKSV = 6, + HDCP_KEYS_STATE_RESERVED = 7, }; enum hdmi_ddc_read_write { @@ -199,6 +193,8 @@ static inline uint32_t HDMI_AUDIO_INFO1_LSV(uint32_t val) #define HDMI_HDCP_CTRL_ENABLE 0x00000001 #define HDMI_HDCP_CTRL_ENCRYPTION_ENABLE 0x00000100 +#define REG_HDMI_HDCP_DEBUG_CTRL 0x00000114 + #define REG_HDMI_HDCP_INT_CTRL 0x00000118 #define REG_HDMI_HDCP_LINK0_STATUS 0x0000011c @@ -211,9 +207,47 @@ static inline uint32_t HDMI_HDCP_LINK0_STATUS_KEY_STATE(enum hdmi_hdcp_key_state return ((val) << HDMI_HDCP_LINK0_STATUS_KEY_STATE__SHIFT) & HDMI_HDCP_LINK0_STATUS_KEY_STATE__MASK; } +#define REG_HDMI_HDCP_DDC_CTRL_0 0x00000120 + +#define REG_HDMI_HDCP_DDC_CTRL_1 0x00000124 + +#define REG_HDMI_HDCP_DDC_STATUS 0x00000128 + +#define REG_HDMI_HDCP_ENTROPY_CTRL0 0x0000012c + +#define REG_HDMI_HDCP_ENTROPY_CTRL1 0x0000025c + #define REG_HDMI_HDCP_RESET 0x00000130 #define HDMI_HDCP_RESET_LINK0_DEAUTHENTICATE 0x00000001 +#define REG_HDMI_HDCP_RCVPORT_DATA0 0x00000134 + +#define REG_HDMI_HDCP_RCVPORT_DATA1 0x00000138 + +#define REG_HDMI_HDCP_RCVPORT_DATA2_0 0x0000013c + +#define REG_HDMI_HDCP_RCVPORT_DATA2_1 0x00000140 + +#define REG_HDMI_HDCP_RCVPORT_DATA3 0x00000144 + +#define REG_HDMI_HDCP_RCVPORT_DATA4 0x00000148 + +#define REG_HDMI_HDCP_RCVPORT_DATA5 0x0000014c + +#define REG_HDMI_HDCP_RCVPORT_DATA6 0x00000150 + +#define REG_HDMI_HDCP_RCVPORT_DATA7 0x00000154 + +#define REG_HDMI_HDCP_RCVPORT_DATA8 0x00000158 + +#define REG_HDMI_HDCP_RCVPORT_DATA9 0x0000015c + +#define REG_HDMI_HDCP_RCVPORT_DATA10 0x00000160 + +#define REG_HDMI_HDCP_RCVPORT_DATA11 0x00000164 + +#define REG_HDMI_HDCP_RCVPORT_DATA12 0x00000168 + #define REG_HDMI_VENSPEC_INFO0 0x0000016c #define REG_HDMI_VENSPEC_INFO1 0x00000170 @@ -329,6 +363,12 @@ static inline uint32_t HDMI_DDC_DATA_INDEX(uint32_t val) } #define HDMI_DDC_DATA_INDEX_WRITE 0x80000000 +#define REG_HDMI_HDCP_SHA_CTRL 0x0000023c + +#define REG_HDMI_HDCP_SHA_STATUS 0x00000240 + +#define REG_HDMI_HDCP_SHA_DATA 0x00000244 + #define REG_HDMI_HPD_INT_STATUS 0x00000250 #define HDMI_HPD_INT_STATUS_INT 0x00000001 #define HDMI_HPD_INT_STATUS_CABLE_DETECTED 0x00000002 @@ -359,6 +399,10 @@ static inline uint32_t HDMI_DDC_REF_REFTIMER(uint32_t val) return ((val) << HDMI_DDC_REF_REFTIMER__SHIFT) & HDMI_DDC_REF_REFTIMER__MASK; } +#define REG_HDMI_HDCP_SW_UPPER_AKSV 0x00000284 + +#define REG_HDMI_HDCP_SW_LOWER_AKSV 0x00000288 + #define REG_HDMI_CEC_STATUS 0x00000298 #define REG_HDMI_CEC_INT 0x0000029c