From patchwork Fri Dec 5 08:35:07 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 5442821 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 46160BEEA8 for ; Fri, 5 Dec 2014 08:36:10 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 030B32035D for ; Fri, 5 Dec 2014 08:36:09 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 2DA3320373 for ; Fri, 5 Dec 2014 08:36:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 624B96E470; Fri, 5 Dec 2014 00:36:07 -0800 (PST) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wg0-f50.google.com (mail-wg0-f50.google.com [74.125.82.50]) by gabe.freedesktop.org (Postfix) with ESMTP id 811E66E4A2 for ; Fri, 5 Dec 2014 00:36:04 -0800 (PST) Received: by mail-wg0-f50.google.com with SMTP id k14so264644wgh.37 for ; Fri, 05 Dec 2014 00:36:03 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8wrYZ8FmhBvhjXJq4oOfsGf+GCi8exkEd3kXcIVj96Q=; b=epfwcv2nKnjgsF0DyD/Am3js04FZ4zZKIvV3UsFGjBIEGV2x+QXO10ioAMgLFDaTNh rdVp+up/oIv0airtedpS/LInX+Jx3aJHySusvYMbVGX8dGjNv+6JymmqQBRMm+JYKmEK U4nWFUzmSmXpX5kTagMunW3oqRuBoXuMXmXoRbFv+l2L1PwXzLuNnALkathKi1jmQzvx M/1zdyUGLVOuv+V6ybLz4P7RnlJD1oI3Dl2LYT/9XlEkq3BhcgNXUcI0GHx9Xg1RAVaH weaJQzXIjLpo7oDaVHEwbcRRrEygX8eZ2Yk9cXPMLR5Bjfep//PBRaTzu2wyS5/FH6H4 qIxw== X-Gm-Message-State: ALoCoQnVsOcqc7v7Kw5CtjC1UQX8amdgD51uJePOVXnQaWk/jXTKAVS3D14+phciiKFehMgJbcey X-Received: by 10.194.238.3 with SMTP id vg3mr21675914wjc.69.1417768563836; Fri, 05 Dec 2014 00:36:03 -0800 (PST) Received: from lmenx321.lme.st.com (LPuteaux-656-1-48-212.w82-127.abo.wanadoo.fr. [82.127.83.212]) by mx.google.com with ESMTPSA id eu8sm1299618wib.21.2014.12.05.00.36.02 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 05 Dec 2014 00:36:03 -0800 (PST) From: Benjamin Gaignard To: dri-devel@lists.freedesktop.org, linaro-mm-sig@lists.linaro.org Subject: [PATCH 9/9] drm: sti: fix delay in VTG programming Date: Fri, 5 Dec 2014 09:35:07 +0100 Message-Id: <1417768507-7538-10-git-send-email-benjamin.gaignard@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1417768507-7538-1-git-send-email-benjamin.gaignard@linaro.org> References: <1417768507-7538-1-git-send-email-benjamin.gaignard@linaro.org> Cc: Benjamin Gaignard X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The HDMI path introduce a delay of 6 pixels. This delay should be take into account while programming VTG for the HDMI. Without this delay, the HDMI active window area is shift of 6 pixel on the right. Set also timing for DVO output. Signed-off-by: Benjamin Gaignard --- drivers/gpu/drm/sti/sti_vtg.c | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/sti/sti_vtg.c b/drivers/gpu/drm/sti/sti_vtg.c index 740d6e3..ce7c0c9 100644 --- a/drivers/gpu/drm/sti/sti_vtg.c +++ b/drivers/gpu/drm/sti/sti_vtg.c @@ -55,6 +55,9 @@ #define VTG_IRQ_TOP BIT(1) #define VTG_IRQ_MASK (VTG_IRQ_TOP | VTG_IRQ_BOTTOM) +/* Delay introduced by the HDMI in nb of pixel */ +#define HDMI_DELAY (6) + /* delay introduced by the Arbitrary Waveform Generator in nb of pixels */ #define AWG_DELAY_HD (-9) #define AWG_DELAY_ED (-8) @@ -133,10 +136,10 @@ static void vtg_set_mode(struct sti_vtg *vtg, writel(tmp, vtg->regs + VTG_VID_TFS); writel(tmp, vtg->regs + VTG_VID_BFS); - /* prepare VTG set 1 and 2 for HDMI and VTG set 3 for HD DAC */ - tmp = (mode->hsync_end - mode->hsync_start) << 16; + /* prepare VTG set 1 for HDMI */ + tmp = (mode->hsync_end - mode->hsync_start + HDMI_DELAY) << 16; + tmp |= HDMI_DELAY; writel(tmp, vtg->regs + VTG_H_HD_1); - writel(tmp, vtg->regs + VTG_H_HD_2); tmp = (mode->vsync_end - mode->vsync_start + 1) << 16; tmp |= 1; @@ -146,6 +149,11 @@ static void vtg_set_mode(struct sti_vtg *vtg, writel(0, vtg->regs + VTG_BOT_V_HD_1); /* prepare VTG set 2 for for HD DCS */ + tmp = (mode->hsync_end - mode->hsync_start) << 16; + writel(tmp, vtg->regs + VTG_H_HD_2); + + tmp = (mode->vsync_end - mode->vsync_start + 1) << 16; + tmp |= 1; writel(tmp, vtg->regs + VTG_TOP_V_VD_2); writel(tmp, vtg->regs + VTG_BOT_V_VD_2); writel(0, vtg->regs + VTG_TOP_V_HD_2); @@ -166,6 +174,17 @@ static void vtg_set_mode(struct sti_vtg *vtg, writel(tmp, vtg->regs + VTG_TOP_V_HD_3); writel(tmp, vtg->regs + VTG_BOT_V_HD_3); + /* Prepare VTG set 4 for DVO */ + tmp = (mode->hsync_end - mode->hsync_start) << 16; + writel(tmp, vtg->regs + VTG_H_HD_4); + + tmp = (mode->vsync_end - mode->vsync_start + 1) << 16; + tmp |= 1; + writel(tmp, vtg->regs + VTG_TOP_V_VD_4); + writel(tmp, vtg->regs + VTG_BOT_V_VD_4); + writel(0, vtg->regs + VTG_TOP_V_HD_4); + writel(0, vtg->regs + VTG_BOT_V_HD_4); + /* mode */ writel(type, vtg->regs + VTG_MODE); }