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[74.96.105.49]) by mx.google.com with ESMTPSA id 43sm18213707qgb.17.2015.01.13.09.47.08 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 13 Jan 2015 09:47:08 -0800 (PST) From: Alex Deucher X-Google-Original-From: Alex Deucher To: dri-devel@lists.freedesktop.org Subject: [PATCH 14/24] radeon: moved HDMI color depth programming to a separate function Date: Tue, 13 Jan 2015 12:46:43 -0500 Message-Id: <1421171213-23977-15-git-send-email-alexander.deucher@amd.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1421171213-23977-1-git-send-email-alexander.deucher@amd.com> References: <1421171213-23977-1-git-send-email-alexander.deucher@amd.com> Cc: Alex Deucher , slava.grigorev@amd.com X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Slava Grigorev Signed-off-by: Slava Grigorev Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/dce3_1_afmt.c | 2 + drivers/gpu/drm/radeon/evergreen_hdmi.c | 69 +++++++++++++++++---------------- drivers/gpu/drm/radeon/r600_hdmi.c | 1 + drivers/gpu/drm/radeon/radeon_audio.c | 22 +++++++++++ drivers/gpu/drm/radeon/radeon_audio.h | 2 + 5 files changed, 62 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/radeon/dce3_1_afmt.c b/drivers/gpu/drm/radeon/dce3_1_afmt.c index 73af518..f11cc15 100644 --- a/drivers/gpu/drm/radeon/dce3_1_afmt.c +++ b/drivers/gpu/drm/radeon/dce3_1_afmt.c @@ -230,6 +230,8 @@ void dce3_1_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *m WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000); + radeon_hdmi_set_color_depth(encoder); + if (ASIC_IS_DCE32(rdev)) { WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */ diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c index 5fffecc..d213444 100644 --- a/drivers/gpu/drm/radeon/evergreen_hdmi.c +++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c @@ -300,45 +300,12 @@ void dce4_set_vbi_packet(struct drm_encoder *encoder, u32 offset) HDMI_GC_CONT); /* send general control packets every frame */ } -/* - * update the info frames with the data from the current display mode - */ -void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode) +void dce4_hdmi_set_color_depth(struct drm_encoder *encoder, u32 offset, int bpc) { struct drm_device *dev = encoder->dev; struct radeon_device *rdev = dev->dev_private; - struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); - struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); - u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; - struct hdmi_avi_infoframe frame; - uint32_t offset; - ssize_t err; uint32_t val; - int bpc = 8; - - if (!dig || !dig->afmt) - return; - - /* Silent, r600_hdmi_enable will raise WARN for us */ - if (!dig->afmt->enabled) - return; - offset = dig->afmt->offset; - - /* hdmi deep color mode general control packets setup, if bpc > 8 */ - if (encoder->crtc) { - struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); - bpc = radeon_crtc->bpc; - } - - /* disable audio prior to setting up hw */ - dig->afmt->pin = radeon_audio_get_pin(encoder); - radeon_audio_enable(rdev, dig->afmt->pin, 0); - - radeon_audio_set_dto(encoder, mode->clock); - radeon_audio_set_vbi_packet(encoder); - - WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000); val = RREG32(HDMI_CONTROL + offset); val &= ~HDMI_DEEP_COLOR_ENABLE; @@ -368,6 +335,40 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode } WREG32(HDMI_CONTROL + offset, val); +} + +/* + * update the info frames with the data from the current display mode + */ +void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode) +{ + struct drm_device *dev = encoder->dev; + struct radeon_device *rdev = dev->dev_private; + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; + u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; + struct hdmi_avi_infoframe frame; + uint32_t offset; + ssize_t err; + + if (!dig || !dig->afmt) + return; + + /* Silent, r600_hdmi_enable will raise WARN for us */ + if (!dig->afmt->enabled) + return; + offset = dig->afmt->offset; + + /* disable audio prior to setting up hw */ + dig->afmt->pin = radeon_audio_get_pin(encoder); + radeon_audio_enable(rdev, dig->afmt->pin, 0); + + radeon_audio_set_dto(encoder, mode->clock); + radeon_audio_set_vbi_packet(encoder); + + WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000); + + radeon_hdmi_set_color_depth(encoder); WREG32(HDMI_INFOFRAME_CONTROL0 + offset, HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c index 7db7e89..8036417 100644 --- a/drivers/gpu/drm/radeon/r600_hdmi.c +++ b/drivers/gpu/drm/radeon/r600_hdmi.c @@ -368,6 +368,7 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod radeon_audio_set_dto(encoder, mode->clock); radeon_audio_set_vbi_packet(encoder); + radeon_hdmi_set_color_depth(encoder); WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */ diff --git a/drivers/gpu/drm/radeon/radeon_audio.c b/drivers/gpu/drm/radeon/radeon_audio.c index 8a8f98c..a7d1bbf 100644 --- a/drivers/gpu/drm/radeon/radeon_audio.c +++ b/drivers/gpu/drm/radeon/radeon_audio.c @@ -87,6 +87,8 @@ void evergreen_hdmi_update_acr(struct drm_encoder *encoder, long offset, const struct radeon_hdmi_acr *acr); void r600_set_vbi_packet(struct drm_encoder *encoder, u32 offset); void dce4_set_vbi_packet(struct drm_encoder *encoder, u32 offset); +void dce4_hdmi_set_color_depth(struct drm_encoder *encoder, + u32 offset, int bpc); static const u32 pin_offsets[7] = { @@ -169,6 +171,7 @@ static struct radeon_audio_funcs dce4_hdmi_funcs = { .set_dto = dce4_hdmi_audio_set_dto, .update_acr = evergreen_hdmi_update_acr, .set_vbi_packet = dce4_set_vbi_packet, + .set_color_depth = dce4_hdmi_set_color_depth, }; static struct radeon_audio_funcs dce4_dp_funcs = { @@ -187,6 +190,7 @@ static struct radeon_audio_funcs dce6_hdmi_funcs = { .write_latency_fields = dce6_afmt_write_latency_fields, .set_dto = dce6_hdmi_audio_set_dto, .set_vbi_packet = dce4_set_vbi_packet, + .set_color_depth = dce4_hdmi_set_color_depth, }; static struct radeon_audio_funcs dce6_dp_funcs = { @@ -573,3 +577,21 @@ void radeon_audio_set_vbi_packet(struct drm_encoder *encoder) if (radeon_encoder->audio && radeon_encoder->audio->set_vbi_packet) radeon_encoder->audio->set_vbi_packet(encoder, dig->afmt->offset); } + +void radeon_hdmi_set_color_depth(struct drm_encoder *encoder) +{ + int bpc = 8; + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; + + if (!dig || !dig->afmt) + return; + + if (encoder->crtc) { + struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); + bpc = radeon_crtc->bpc; + } + + if (radeon_encoder->audio && radeon_encoder->audio->set_color_depth) + radeon_encoder->audio->set_color_depth(encoder, dig->afmt->offset, bpc); +} diff --git a/drivers/gpu/drm/radeon/radeon_audio.h b/drivers/gpu/drm/radeon/radeon_audio.h index 7cdbd7f..f179e56 100644 --- a/drivers/gpu/drm/radeon/radeon_audio.h +++ b/drivers/gpu/drm/radeon/radeon_audio.h @@ -58,6 +58,7 @@ struct radeon_audio_funcs void (*update_acr)(struct drm_encoder *encoder, long offset, const struct radeon_hdmi_acr *acr); void (*set_vbi_packet)(struct drm_encoder *encoder, u32 offset); + void (*set_color_depth)(struct drm_encoder *encoder, u32 offset, int bpc); }; int radeon_audio_init(struct radeon_device *rdev); @@ -81,5 +82,6 @@ void radeon_update_avi_infoframe(struct drm_encoder *encoder, void *buffer, size_t size); void radeon_audio_update_acr(struct drm_encoder *encoder, unsigned int clock); void radeon_audio_set_vbi_packet(struct drm_encoder *encoder); +void radeon_hdmi_set_color_depth(struct drm_encoder *encoder); #endif