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Thu, 22 Jan 2015 05:55:56 -0600 Received: from STOREXDAG03.amd.com (10.1.13.12) by SATLEXDAG02.amd.com (10.181.40.5) with Microsoft SMTP Server (TLS) id 14.3.195.1; Thu, 22 Jan 2015 06:55:53 -0500 Received: from AMD (10.20.0.84) by storexdag03.amd.com (10.1.13.12) with Microsoft SMTP Server (TLS) id 14.3.195.1; Thu, 22 Jan 2015 06:55:51 -0500 From: Oded Gabbay To: Subject: [PATCH] drm/amdkfd: Fix sparse errors Date: Thu, 22 Jan 2015 13:55:27 +0200 Message-ID: <1421927727-5881-1-git-send-email-oded.gabbay@amd.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 X-Originating-IP: [10.20.0.84] X-EOPAttributedMessage: 0 Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) Authentication-Results: spf=none (sender IP is 165.204.84.222) smtp.mailfrom=Oded.Gabbay@amd.com; X-Forefront-Antispam-Report: CIP:165.204.84.222; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(428002)(189002)(199003)(2351001)(105586002)(107886001)(106466001)(229853001)(575784001)(86362001)(19580405001)(19580395003)(97736003)(77096005)(68736005)(50986999)(101416001)(92566002)(87936001)(64706001)(47776003)(110136001)(450100001)(48376002)(50466002)(33646002)(46102003)(62966003)(36756003)(77156002)(50226001); DIR:OUT; SFP:1102; SCL:1; SRVR:DM2PR0201MB1087; H:atltwp02.amd.com; FPR:; SPF:None; MLV:sfv; PTR:InfoDomainNonexistent; MX:1; A:1; LANG:en; X-DmarcAction-Test: None X-Microsoft-Antispam: UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:(3005004);SRVR:DM2PR0201MB1087; X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004); SRVR:DM2PR0201MB1087; X-Forefront-PRVS: 0464DBBBC4 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:; SRVR:DM2PR0201MB1087; X-OriginatorOrg: amd4.onmicrosoft.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jan 2015 11:55:54.9699 (UTC) X-MS-Exchange-CrossTenant-Id: fde4dada-be84-483f-92cc-e026cbee8e96 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=fde4dada-be84-483f-92cc-e026cbee8e96; Ip=[165.204.84.222] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM2PR0201MB1087 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Oded Gabbay Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 16 ++++++------- .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 28 ++-------------------- .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.h | 20 +++++++++++++--- 3 files changed, 27 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 732087dc..5c50aa8 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -141,8 +141,6 @@ static int kfd_ioctl_get_version(struct file *filep, struct kfd_process *p, static int set_queue_properties_from_user(struct queue_properties *q_properties, struct kfd_ioctl_create_queue_args *args) { - void *tmp; - if (args->queue_percentage > KFD_MAX_QUEUE_PERCENTAGE) { pr_err("kfd: queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n"); return -EINVAL; @@ -180,16 +178,18 @@ static int set_queue_properties_from_user(struct queue_properties *q_properties, return -EFAULT; } - tmp = (void *)(uintptr_t)args->eop_buffer_address; - if (tmp != NULL && - !access_ok(VERIFY_WRITE, tmp, sizeof(uint32_t))) { + if (args->eop_buffer_address && + !access_ok(VERIFY_WRITE, + (const void __user *) args->eop_buffer_address, + sizeof(uint32_t))) { pr_debug("kfd: can't access eop buffer"); return -EFAULT; } - tmp = (void *)(uintptr_t)args->ctx_save_restore_address; - if (tmp != NULL && - !access_ok(VERIFY_WRITE, tmp, sizeof(uint32_t))) { + if (args->ctx_save_restore_address && + !access_ok(VERIFY_WRITE, + (const void __user *) args->ctx_save_restore_address, + sizeof(uint32_t))) { pr_debug("kfd: can't access ctx save restore buffer"); return -EFAULT; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 99e2dbb..b189f97 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -62,12 +62,6 @@ enum KFD_MQD_TYPE get_mqd_type_from_queue_type(enum kfd_queue_type type) return KFD_MQD_TYPE_CP; } -inline unsigned int get_pipes_num(struct device_queue_manager *dqm) -{ - BUG_ON(!dqm || !dqm->dev); - return dqm->dev->shared_resources.compute_pipe_count; -} - static inline unsigned int get_first_pipe(struct device_queue_manager *dqm) { BUG_ON(!dqm); @@ -79,25 +73,6 @@ static inline unsigned int get_pipes_num_cpsch(void) return PIPE_PER_ME_CP_SCHEDULING; } -inline unsigned int -get_sh_mem_bases_nybble_64(struct kfd_process_device *pdd) -{ - uint32_t nybble; - - nybble = (pdd->lds_base >> 60) & 0x0E; - - return nybble; -} - -inline unsigned int get_sh_mem_bases_32(struct kfd_process_device *pdd) -{ - unsigned int shared_base; - - shared_base = (pdd->lds_base >> 16) & 0xFF; - - return shared_base; -} - void program_sh_mem_settings(struct device_queue_manager *dqm, struct qcm_process_device *qpd) { @@ -336,7 +311,8 @@ static int update_queue(struct device_queue_manager *dqm, struct queue *q) BUG_ON(!dqm || !q || !q->mqd); mutex_lock(&dqm->lock); - mqd = dqm->ops.get_mqd_manager(dqm, q->properties.type); + mqd = dqm->ops.get_mqd_manager(dqm, + get_mqd_type_from_queue_type(q->properties.type)); if (mqd == NULL) { mutex_unlock(&dqm->lock); return -ENOMEM; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h index 1934795..e7b17b2 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h @@ -160,10 +160,24 @@ void device_queue_manager_init_cik(struct device_queue_manager_ops *ops); void device_queue_manager_init_vi(struct device_queue_manager_ops *ops); void program_sh_mem_settings(struct device_queue_manager *dqm, struct qcm_process_device *qpd); -inline unsigned int get_sh_mem_bases_32(struct kfd_process_device *qpd); -inline unsigned int get_sh_mem_bases_nybble_64(struct kfd_process_device *pdd); int init_pipelines(struct device_queue_manager *dqm, unsigned int pipes_num, unsigned int first_pipe); -inline unsigned int get_pipes_num(struct device_queue_manager *dqm); + +extern inline unsigned int get_sh_mem_bases_32(struct kfd_process_device *pdd) +{ + return (pdd->lds_base >> 16) & 0xFF; +} + +extern inline unsigned int +get_sh_mem_bases_nybble_64(struct kfd_process_device *pdd) +{ + return (pdd->lds_base >> 60) & 0x0E; +} + +extern inline unsigned int get_pipes_num(struct device_queue_manager *dqm) +{ + BUG_ON(!dqm || !dqm->dev); + return dqm->dev->shared_resources.compute_pipe_count; +} #endif /* KFD_DEVICE_QUEUE_MANAGER_H_ */