From patchwork Fri Jan 23 08:03:15 2015
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
X-Patchwork-Submitter: Hyungwon Hwang <human.hwang@samsung.com>
X-Patchwork-Id: 5691391
Return-Path: <dri-devel-bounces@lists.freedesktop.org>
X-Original-To: patchwork-dri-devel@patchwork.kernel.org
Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org
Received: from mail.kernel.org (mail.kernel.org [198.145.29.136])
	by patchwork2.web.kernel.org (Postfix) with ESMTP id 591ACC058D
	for <patchwork-dri-devel@patchwork.kernel.org>;
	Fri, 23 Jan 2015 08:03:33 +0000 (UTC)
Received: from mail.kernel.org (localhost [127.0.0.1])
	by mail.kernel.org (Postfix) with ESMTP id CCEDB20149
	for <patchwork-dri-devel@patchwork.kernel.org>;
	Fri, 23 Jan 2015 08:03:31 +0000 (UTC)
Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177])
	by mail.kernel.org (Postfix) with ESMTP id E86062012E
	for <patchwork-dri-devel@patchwork.kernel.org>;
	Fri, 23 Jan 2015 08:03:29 +0000 (UTC)
Received: from gabe.freedesktop.org (localhost [127.0.0.1])
	by gabe.freedesktop.org (Postfix) with ESMTP id A20D06E4A1;
	Fri, 23 Jan 2015 00:03:28 -0800 (PST)
X-Original-To: dri-devel@lists.freedesktop.org
Delivered-To: dri-devel@lists.freedesktop.org
Received: from mailout1.samsung.com (mailout1.samsung.com [203.254.224.24])
	by gabe.freedesktop.org (Postfix) with ESMTP id 6F5C66E4A1
	for <dri-devel@lists.freedesktop.org>;
	Fri, 23 Jan 2015 00:03:26 -0800 (PST)
Received: from epcpsbgr4.samsung.com
	(u144.gpu120.samsung.co.kr [203.254.230.144])
	by mailout1.samsung.com (Oracle Communications Messaging Server
	7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011))
	with ESMTP id <0NIM0036QEDPMN20@mailout1.samsung.com> for
	dri-devel@lists.freedesktop.org; Fri, 23 Jan 2015 17:03:25 +0900 (KST)
Received: from epcpsbgm1.samsung.com ( [172.20.52.113])
	by epcpsbgr4.samsung.com (EPCPMTA) with SMTP id 47.FD.18167.A4002C45;
	Fri, 23 Jan 2015 17:03:22 +0900 (KST)
X-AuditID: cbfee690-f79ab6d0000046f7-06-54c2004adbad
Received: from epmmp2 ( [203.254.227.17])	by epcpsbgm1.samsung.com (EPCPMTA)
	with SMTP id 2F.8F.20081.A4002C45;
	Fri, 23 Jan 2015 17:03:22 +0900 (KST)
Received: from localhost.localdomain ([10.252.82.145])
	by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01
	(7.0.4.24.0) 64bit (built Nov 17 2011))
	with ESMTPA id <0NIM00HOWEDHK630@mmp2.samsung.com>; Fri,
	23 Jan 2015 17:03:22 +0900 (KST)
From: Hyungwon Hwang <human.hwang@samsung.com>
To: dri-devel@lists.freedesktop.org
Subject: [PATCH] drm/panel: add s6e3ha2 LCD panel driver
Date: Fri, 23 Jan 2015 17:03:15 +0900
Message-id: <1422000195-11839-1-git-send-email-human.hwang@samsung.com>
X-Mailer: git-send-email 1.9.1
X-Brightmail-Tracker: 
 H4sIAAAAAAAAA+NgFlrDLMWRmVeSWpSXmKPExsWyRsSkUNeL4VCIwYY/NhbXz9tZXPn6ns1i
	6Yw+VotJ9yewWBz/dJDFgdXjfvdxJo++LasYA5iiuGxSUnMyy1KL9O0SuDK2L+tlLPjWxFix
	ZIVsA+OJ3C5GTg4JAROJTV92MkPYYhIX7q1n62Lk4hASWMoo8frCZRaYopcr5jFDJKYzSlxc
	MZUJwmljkmje9Z0JpIpNQE9iwbUf7CC2iICyxN+JqxhBipgFJjNKdO/tAEsIC1hIPF55GKyB
	RUBV4smzi4wgNq+Au8THHdfYINbJSZw8NpkVpFlC4DabxL+bEAkWAQGJb5MPAd3EAZSQldh0
	AOpuSYmDK26wTGAUXMDIsIpRNLUguaA4Kb3IRK84Mbe4NC9dLzk/dxMjMBBP/3s2YQfjvQPW
	hxgFOBiVeHgbthwMEWJNLCuuzD3EaAq0YSKzlGhyPjDc80riDY3NjCxMTUyNjcwtzZTEeV9L
	/QwWEkhPLEnNTk0tSC2KLyrNSS0+xMjEwSnVwNh1wu4mmyL7dHmRPWq2G32/1gW/UG2/Et2Z
	eedmjvrlj8s8vRPagmJ09pjGHPTt0nT5uZR1T1XSL86l/GX3bmfGC6l3Tgj4OIk1VTBrzpOd
	s6bND2O7EHv624dqZlH3Gxa3/Wfc7v0ml7nVYMX0KyvNrl1bOSl25lrV+WzhAlkzTwRzfQn/
	lKbEUpyRaKjFXFScCAB/6sT6PwIAAA==
X-Brightmail-Tracker: 
 H4sIAAAAAAAAA+NgFvrGLMWRmVeSWpSXmKPExsVy+t9jQV0vhkMhBq9u61pcP29nceXrezaL
	pTP6WC0m3Z/AYnH800EWB1aP+93HmTz6tqxiDGCKamC0yUhNTEktUkjNS85PycxLt1XyDo53
	jjc1MzDUNbS0MFdSyEvMTbVVcvEJ0HXLzAFap6RQlphTChQKSCwuVtK3wzQhNMRN1wKmMULX
	NyQIrsfIAA0krGHM2L6sl7HgWxNjxZIVsg2MJ3K7GDk5JARMJF6umMcMYYtJXLi3nq2LkYtD
	SGA6o8TFFVOZIJw2JonmXd+ZQKrYBPQkFlz7wQ5iiwgoS/yduIoRpIhZYDKjRPfeDrCEsICF
	xOOVh8EaWARUJZ48u8gIYvMKuEt83HGNDWKdnMTJY5NZJzByL2BkWMUomlqQXFCclJ5rqFec
	mFtcmpeul5yfu4kRHObPpHYwrmywOMQowMGoxMPbsOVgiBBrYllxZe4hRgkOZiUR3rgvQCHe
	lMTKqtSi/Pii0pzU4kOMpkDbJzJLiSbnA2MwryTe0NjEzMjSyNzQwsjYXEmcV8m+LURIID2x
	JDU7NbUgtQimj4mDU6qB0faB/+XsFMW5z14kT45Vav/FsIflh8Xc80FPgqbO3DO5xYLlWtdZ
	3dvd4V83/jU4eyyxQr+Dp/vkosZH7NlZWk23O74fuMVyXmr/XXbGTYe+MKg+jjq/NzD1dMf1
	z33TfnhVnWM0SJgcbNBWKtth+0PylOHDL/66ji8PRTFo71X+9Jnvzqw7+kosxRmJhlrMRcWJ
	ALNuKviJAgAA
DLP-Filter: Pass
X-MTR: 20000000000000000@CPGS
X-CFilter-Loop: Reflected
Cc: Sangbae Lee <sangbae90.lee@samsung.com>,
	Donghwa Lee <dh09.lee@samsung.com>,
	Hyungwon Hwang <human.hwang@samsung.com>
X-BeenThere: dri-devel@lists.freedesktop.org
X-Mailman-Version: 2.1.18
Precedence: list
List-Id: Direct Rendering Infrastructure - Development
	<dri-devel.lists.freedesktop.org>
List-Unsubscribe: <http://lists.freedesktop.org/mailman/options/dri-devel>,
	<mailto:dri-devel-request@lists.freedesktop.org?subject=unsubscribe>
List-Archive: <http://lists.freedesktop.org/archives/dri-devel>
List-Post: <mailto:dri-devel@lists.freedesktop.org>
List-Help: <mailto:dri-devel-request@lists.freedesktop.org?subject=help>
List-Subscribe: <http://lists.freedesktop.org/mailman/listinfo/dri-devel>,
	<mailto:dri-devel-request@lists.freedesktop.org?subject=subscribe>
MIME-Version: 1.0
Errors-To: dri-devel-bounces@lists.freedesktop.org
Sender: "dri-devel" <dri-devel-bounces@lists.freedesktop.org>
X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED,
	T_RP_MATCHES_RCVD,
	UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1
X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org
X-Virus-Scanned: ClamAV using ClamSMTP

From: Donghwa Lee <dh09.lee@samsung.com>

This patch adds MIPI-DSI based S6E3HA2 panel driver. This panel has
1440x2560 resolution in 5.7-inch physical panel. This panel was
selected for Galaxy Note 4.

Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
Cc: Inki Dae <inki.dae@samsung.com>
Cc: Sangbae Lee <sangbae90.lee@samsung.com>
---
 .../devicetree/bindings/panel/samsung,s6e3ha2.txt  |  49 ++
 drivers/gpu/drm/panel/Kconfig                      |   6 +
 drivers/gpu/drm/panel/Makefile                     |   1 +
 drivers/gpu/drm/panel/panel-s6e3ha2.c              | 513 +++++++++++++++++++++
 4 files changed, 569 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/panel/samsung,s6e3ha2.txt
 create mode 100644 drivers/gpu/drm/panel/panel-s6e3ha2.c

diff --git a/Documentation/devicetree/bindings/panel/samsung,s6e3ha2.txt b/Documentation/devicetree/bindings/panel/samsung,s6e3ha2.txt
new file mode 100644
index 0000000..098089b
--- /dev/null
+++ b/Documentation/devicetree/bindings/panel/samsung,s6e3ha2.txt
@@ -0,0 +1,49 @@
+Samsung S6E63J0X03 1.63" 320x320 TFT LCD panel
+
+Required properties:
+  - compatible: "samsung,s6e63j0x03"
+  - reg: the virtual channel number of a DSI peripheral
+  - vdd3-supply: core voltage supply
+  - vci-supply: voltage supply for analog circuits
+  - reset-gpios: a GPIO spec for the reset pin
+  - lcd-en-gpios: a GPIO spec for the LCD enable pin
+  - te-gpios: a GPIO spec for the tearing effect synchronization signal gpio pin
+
+Optional properties:
+  - display-timings: timings for the connected panel as described by [1]
+  - panel-width-mm: physical panel width [mm]
+  - panel-height-mm: physical panel height [mm]
+
+The device node can contain one 'port' child node with one child
+'endpoint' node, according to the bindings defined in [2]. This
+node should describe panel's video bus.
+
+[1]: Documentation/devicetree/bindings/video/display-timing.txt
+[2]: Documentation/devicetree/bindings/media/video-interfaces.txt
+
+Example:
+
+panel@0 {
+	compatible = "samsung,s6e3ha2";
+	reg = <0>;
+	vdd3-supply = <&ldo27_reg>;
+	vci-supply = <&ldo28_reg>;
+	reset-gpios = <&gpg0 0 0>;
+	lcd-en-gpios = <&gpf1 5 0>;
+	te-gpios = <&gpf1 3 1>;
+	panel-width-mm = <71>;
+	panel-height-mm = <125>;
+
+	display-timings {
+		timing-0 {
+			clock-frequency = <0>;
+			hactive = <1440>;
+			vactive = <2560>;
+			hfront-porch = <1>;
+			hback-porch = <1>;
+			hsync-len = <1>;
+			vfront-porch = <1>;
+			vback-porch = <15>;
+			vsync-len = <1>;
+		};
+	};
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index dec60b2..451b5f3 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -46,4 +46,10 @@ config DRM_PANEL_S6E63J0X03
 	select DRM_MIPI_DSI
 	select VIDEOMODE_HELPERS
 
+config DRM_PANEL_S6E3HA2
+	tristate "S6E3HA2 DSI video mode panel"
+	depends on OF
+	select DRM_MIPI_DSI
+	select VIDEOMODE_HELPERS
+
 endmenu
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 6467be7..7bd7b84 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -3,3 +3,4 @@ obj-$(CONFIG_DRM_PANEL_LD9040) += panel-ld9040.o
 obj-$(CONFIG_DRM_PANEL_S6E8AA0) += panel-s6e8aa0.o
 obj-$(CONFIG_DRM_PANEL_S6E63J0X03) += panel-s6e63j0x03.o
 obj-$(CONFIG_DRM_PANEL_SHARP_LQ101R1SX01) += panel-sharp-lq101r1sx01.o
+obj-$(CONFIG_DRM_PANEL_S6E3HA2) += panel-s6e3ha2.o
diff --git a/drivers/gpu/drm/panel/panel-s6e3ha2.c b/drivers/gpu/drm/panel/panel-s6e3ha2.c
new file mode 100644
index 0000000..9664b72
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-s6e3ha2.c
@@ -0,0 +1,513 @@
+/*
+ * MIPI-DSI based s6e3ha2 AMOLED LCD 5.3 inch panel driver.
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd
+ *
+ * Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <drm/drmP.h>
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_panel.h>
+
+#include <linux/of_gpio.h>
+#include <linux/gpio.h>
+
+#include <linux/gpio/consumer.h>
+#include <linux/regulator/consumer.h>
+
+#include <video/mipi_display.h>
+#include <video/of_videomode.h>
+#include <video/videomode.h>
+
+struct s6e3ha2 {
+	struct device *dev;
+	struct drm_panel panel;
+
+	struct regulator_bulk_data supplies[2];
+	struct gpio_desc *reset_gpio;
+	struct gpio_desc *lcd_en_gpio;
+	struct videomode vm;
+	u32 width_mm;
+	u32 height_mm;
+
+	/* This field is tested by functions directly accessing DSI bus before
+	 * transfer, transfer is skipped if it is set. In case of transfer
+	 * failure or unexpected response the field is set to error value.
+	 * Such construct allows to eliminate many checks in higher level
+	 * functions.
+	 */
+	int error;
+};
+
+static inline struct s6e3ha2 *panel_to_s6e3ha2(struct drm_panel *panel)
+{
+	return container_of(panel, struct s6e3ha2, panel);
+}
+
+static void s6e3ha2_clear_error(struct s6e3ha2 *ctx)
+{
+	ctx->error = 0;
+}
+
+static void s6e3ha2_dcs_write(struct s6e3ha2 *ctx, const u8 cmd,
+		const u8 *data, size_t len)
+{
+	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
+	ssize_t ret;
+
+	if (ctx->error < 0)
+		return;
+
+	ret = mipi_dsi_dcs_write(dsi, cmd, (const void *)data, len);
+	if (ret < 0) {
+		dev_err(ctx->dev, "error %zd writing dcs seq: %*ph\n", ret, len,
+			data);
+		ctx->error = ret;
+	}
+}
+
+#define s6e3ha2_dcs_write_seq_static(ctx, cmd, seq...) \
+({\
+	static const u8 c = cmd;\
+	static const u8 d[] = { seq };\
+	s6e3ha2_dcs_write(ctx, c, d, ARRAY_SIZE(d));\
+})
+
+static void s6e3ha2_test_key_on_f0(struct s6e3ha2 *ctx)
+{
+	s6e3ha2_dcs_write_seq_static(ctx, 0xf0, 0x5a, 0x5a);
+}
+
+static void s6e3ha2_test_key_off_f0(struct s6e3ha2 *ctx)
+{
+	s6e3ha2_dcs_write_seq_static(ctx, 0xf0, 0xa5, 0xa5);
+}
+
+static void s6e3ha2_test_key_on_fc(struct s6e3ha2 *ctx)
+{
+	s6e3ha2_dcs_write_seq_static(ctx, 0xfc, 0x5a, 0x5a);
+}
+
+static void s6e3ha2_test_key_off_fc(struct s6e3ha2 *ctx)
+{
+	s6e3ha2_dcs_write_seq_static(ctx, 0xfc, 0xa5, 0xa5);
+}
+
+static void s6e3ha2_single_dsi_set1(struct s6e3ha2 *ctx)
+{
+	s6e3ha2_dcs_write_seq_static(ctx, 0xf2, 0x67);
+}
+
+static void s6e3ha2_single_dsi_set2(struct s6e3ha2 *ctx)
+{
+	s6e3ha2_dcs_write_seq_static(ctx, 0xf9, 0x09);
+}
+
+static void s6e3ha2_calibration_set1(struct s6e3ha2 *ctx)
+{
+	s6e3ha2_dcs_write_seq_static(ctx, 0xb0, 0x02);
+}
+
+static void s6e3ha2_calibration_set2(struct s6e3ha2 *ctx)
+{
+	s6e3ha2_dcs_write_seq_static(ctx, 0xf2, 0xc5);
+}
+
+static void s6e3ha2_calibration_set3(struct s6e3ha2 *ctx)
+{
+	s6e3ha2_dcs_write_seq_static(ctx, 0xfd, 0x1c);
+}
+
+static void s6e3ha2_calibration_set4(struct s6e3ha2 *ctx)
+{
+	s6e3ha2_dcs_write_seq_static(ctx, 0xb0, 0x01);
+}
+
+static void s6e3ha2_calibration_set5(struct s6e3ha2 *ctx)
+{
+	s6e3ha2_dcs_write_seq_static(ctx, 0xfe, 0x39);
+}
+
+static void s6e3ha2_calibration_set6(struct s6e3ha2 *ctx)
+{
+	s6e3ha2_dcs_write_seq_static(ctx, 0xfe, 0xa0);
+}
+
+static void s6e3ha2_calibration_set7(struct s6e3ha2 *ctx)
+{
+	s6e3ha2_dcs_write_seq_static(ctx, 0xfe, 0x20);
+}
+
+static void s6e3ha2_calibration_set8(struct s6e3ha2 *ctx)
+{
+	s6e3ha2_dcs_write_seq_static(ctx, 0xce, 0x03, 0x3b, 0x14, 0x6d);
+}
+
+static void s6e3ha2_calibration_set9(struct s6e3ha2 *ctx)
+{
+	s6e3ha2_dcs_write_seq_static(ctx, 0xb0, 0x0c);
+}
+
+static void s6e3ha2_calibration_set10(struct s6e3ha2 *ctx)
+{
+	s6e3ha2_dcs_write_seq_static(ctx, 0xce, 0xc5);
+}
+
+static void s6e3ha2_aor_control(struct s6e3ha2 *ctx)
+{
+	s6e3ha2_dcs_write_seq_static(ctx, 0xb2, 0x03, 0x10);
+}
+
+static void s6e3ha2_caps_elvss_set(struct s6e3ha2 *ctx)
+{
+	s6e3ha2_dcs_write_seq_static(ctx, 0xb6, 0x9c, 0x0a);
+}
+
+static void s6e3ha2_acl_off(struct s6e3ha2 *ctx)
+{
+	s6e3ha2_dcs_write_seq_static(ctx, 0x55, 0x00);
+}
+
+static void s6e3ha2_acl_off_opr(struct s6e3ha2 *ctx)
+{
+	s6e3ha2_dcs_write_seq_static(ctx, 0xb5, 0x40);
+}
+
+static void s6e3ha2_test_global(struct s6e3ha2 *ctx)
+{
+	s6e3ha2_dcs_write_seq_static(ctx, 0xb0, 0x07);
+}
+
+static void s6e3ha2_test(struct s6e3ha2 *ctx)
+{
+	s6e3ha2_dcs_write_seq_static(ctx, 0xb8, 0x19);
+}
+
+static void s6e3ha2_touch_hsync_on(struct s6e3ha2 *ctx)
+{
+	s6e3ha2_dcs_write_seq_static(ctx,
+			0xbd, 0x11, 0x11, 0x02, 0x16, 0x02, 0x16);
+}
+
+static void s6e3ha2_pentile_control(struct s6e3ha2 *ctx)
+{
+	s6e3ha2_dcs_write_seq_static(ctx, 0xc0, 0x00, 0x00, 0xd8, 0xd8);
+}
+
+static void s6e3ha2_poc_setting(struct s6e3ha2 *ctx)
+{
+	s6e3ha2_dcs_write_seq_static(ctx, 0xc3, 0xc0, 0x00, 0x33);
+}
+
+static void s6e3ha2_pcd_set_off(struct s6e3ha2 *ctx)
+{
+	s6e3ha2_dcs_write_seq_static(ctx, 0xcc, 0x40, 0x51);
+}
+
+static void s6e3ha2_err_fg_set(struct s6e3ha2 *ctx)
+{
+	s6e3ha2_dcs_write_seq_static(ctx, 0xed, 0x44);
+}
+
+static void s6e3ha2_hbm_off(struct s6e3ha2 *ctx)
+{
+	s6e3ha2_dcs_write_seq_static(ctx, 0x53, 0x00);
+}
+
+static void s6e3ha2_te_start_setting(struct s6e3ha2 *ctx)
+{
+	s6e3ha2_dcs_write_seq_static(ctx, 0xb9, 0x10, 0x09, 0xff, 0x00, 0x09);
+}
+
+
+static void s6e3ha2_gamma_update(struct s6e3ha2 *ctx)
+{
+	s6e3ha2_dcs_write_seq_static(ctx, 0xf7, 0x03);
+}
+
+static void s6e3ha2_brightness_set(struct s6e3ha2 *ctx)
+{
+	s6e3ha2_dcs_write_seq_static(ctx,
+		0xca, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x80, 0x80, 0x80,
+		0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+		0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+		0x80, 0x80, 0x80, 0x80, 0x00, 0x00);
+}
+
+static void s6e3ha2_panel_init(struct s6e3ha2 *ctx)
+{
+	s6e3ha2_dcs_write_seq_static(ctx, MIPI_DCS_EXIT_SLEEP_MODE);
+
+	usleep_range(5000, 6000);
+
+	s6e3ha2_test_key_on_f0(ctx);
+	s6e3ha2_single_dsi_set1(ctx);
+	s6e3ha2_single_dsi_set2(ctx);
+
+	/* calibration enable */
+	s6e3ha2_test_key_on_fc(ctx);
+	s6e3ha2_calibration_set1(ctx);
+	s6e3ha2_calibration_set2(ctx);
+	s6e3ha2_calibration_set3(ctx);
+	s6e3ha2_calibration_set4(ctx);
+	s6e3ha2_calibration_set5(ctx);
+	s6e3ha2_calibration_set6(ctx);
+	s6e3ha2_calibration_set7(ctx);
+	s6e3ha2_calibration_set8(ctx);
+	s6e3ha2_calibration_set9(ctx);
+	s6e3ha2_calibration_set10(ctx);
+
+	msleep(120);
+
+	/* common setting */
+	s6e3ha2_dcs_write_seq_static(ctx, MIPI_DCS_SET_TEAR_ON);
+
+	s6e3ha2_touch_hsync_on(ctx);
+	s6e3ha2_pentile_control(ctx);
+	s6e3ha2_poc_setting(ctx);
+	s6e3ha2_test_key_off_fc(ctx);
+
+	/* pcd setting off for TB */
+	s6e3ha2_pcd_set_off(ctx);
+	s6e3ha2_err_fg_set(ctx);
+	s6e3ha2_te_start_setting(ctx);
+
+	/* brightness setting */
+	s6e3ha2_brightness_set(ctx);
+	s6e3ha2_aor_control(ctx);
+	s6e3ha2_caps_elvss_set(ctx);
+	s6e3ha2_gamma_update(ctx);
+	s6e3ha2_acl_off(ctx);
+	s6e3ha2_acl_off_opr(ctx);
+	s6e3ha2_hbm_off(ctx);
+
+	/* elvss temp compensation */
+	s6e3ha2_test_global(ctx);
+	s6e3ha2_test(ctx);
+
+	s6e3ha2_test_key_off_f0(ctx);
+	s6e3ha2_dcs_write_seq_static(ctx, MIPI_DCS_SET_DISPLAY_ON);
+}
+
+static int s6e3ha2_power_off(struct s6e3ha2 *ctx)
+{
+	return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
+}
+
+static int s6e3ha2_disable(struct drm_panel *panel)
+{
+	return 0;
+}
+
+static int s6e3ha2_unprepare(struct drm_panel *panel)
+{
+	struct s6e3ha2 *ctx = panel_to_s6e3ha2(panel);
+
+	s6e3ha2_dcs_write_seq_static(ctx, MIPI_DCS_ENTER_SLEEP_MODE);
+	s6e3ha2_dcs_write_seq_static(ctx, MIPI_DCS_SET_DISPLAY_OFF);
+	msleep(40);
+
+	s6e3ha2_clear_error(ctx);
+
+	return s6e3ha2_power_off(ctx);
+}
+
+static int s6e3ha2_power_on(struct s6e3ha2 *ctx)
+{
+	int ret;
+
+	ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
+	if (ret < 0)
+		return ret;
+
+	msleep(25);
+
+	gpiod_set_value(ctx->lcd_en_gpio, 0);
+	usleep_range(5000, 6000);
+	gpiod_set_value(ctx->lcd_en_gpio, 1);
+
+	gpiod_set_value(ctx->reset_gpio, 1);
+	usleep_range(5000, 6000);
+	gpiod_set_value(ctx->reset_gpio, 0);
+	usleep_range(5000, 6000);
+	gpiod_set_value(ctx->reset_gpio, 1);
+	usleep_range(5000, 6000);
+
+	return 0;
+}
+static int s6e3ha2_prepare(struct drm_panel *panel)
+{
+	struct s6e3ha2 *ctx = panel_to_s6e3ha2(panel);
+	int ret;
+
+	ret = s6e3ha2_power_on(ctx);
+	if (ret < 0)
+		return ret;
+
+	s6e3ha2_panel_init(ctx);
+	if (ctx->error < 0)
+		s6e3ha2_unprepare(panel);
+
+	return ret;
+}
+
+static int s6e3ha2_enable(struct drm_panel *panel)
+{
+	return 0;
+}
+
+static int s6e3ha2_get_modes(struct drm_panel *panel)
+{
+	struct drm_connector *connector = panel->connector;
+	struct s6e3ha2 *ctx = panel_to_s6e3ha2(panel);
+	struct drm_display_mode *mode;
+
+	mode = drm_mode_create(connector->dev);
+	if (!mode) {
+		DRM_ERROR("failed to create a new display mode\n");
+		return 0;
+	}
+
+	drm_display_mode_from_videomode(&ctx->vm, mode);
+	mode->width_mm = ctx->width_mm;
+	mode->height_mm = ctx->height_mm;
+	connector->display_info.width_mm = mode->width_mm;
+	connector->display_info.height_mm = mode->height_mm;
+
+	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
+	drm_mode_probed_add(connector, mode);
+
+	return 1;
+}
+
+static const struct drm_panel_funcs s6e3ha2_drm_funcs = {
+	.disable = s6e3ha2_disable,
+	.unprepare = s6e3ha2_unprepare,
+	.prepare = s6e3ha2_prepare,
+	.enable = s6e3ha2_enable,
+	.get_modes = s6e3ha2_get_modes,
+};
+
+static int s6e3ha2_parse_dt(struct s6e3ha2 *ctx)
+{
+	struct device *dev = ctx->dev;
+	struct device_node *np = dev->of_node;
+	int ret;
+
+	ret = of_get_videomode(np, &ctx->vm, 0);
+	if (ret < 0)
+		return ret;
+
+	of_property_read_u32(np, "panel-width-mm", &ctx->width_mm);
+	of_property_read_u32(np, "panel-height-mm", &ctx->height_mm);
+
+	return 0;
+}
+
+static int s6e3ha2_probe(struct mipi_dsi_device *dsi)
+{
+	struct device *dev = &dsi->dev;
+	struct s6e3ha2 *ctx;
+	int ret;
+
+	ctx = devm_kzalloc(dev, sizeof(struct s6e3ha2), GFP_KERNEL);
+	if (!ctx)
+		return -ENOMEM;
+
+	mipi_dsi_set_drvdata(dsi, ctx);
+
+	ctx->dev = dev;
+
+	dsi->lanes = 4;
+	dsi->format = MIPI_DSI_FMT_RGB888;
+	dsi->mode_flags = MIPI_DSI_CLOCK_NON_CONTINUOUS;
+
+	ret = s6e3ha2_parse_dt(ctx);
+	if (ret < 0)
+		return ret;
+
+	ctx->supplies[0].supply = "vdd3";
+	ctx->supplies[1].supply = "vci";
+
+	ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ctx->supplies),
+				      ctx->supplies);
+	if (ret < 0) {
+		dev_err(dev, "failed to get regulators: %d\n", ret);
+		return ret;
+	}
+
+	ctx->reset_gpio = devm_gpiod_get(dev, "reset");
+	if (IS_ERR(ctx->reset_gpio)) {
+		dev_err(dev, "cannot get reset-gpios %ld\n",
+			PTR_ERR(ctx->reset_gpio));
+		return PTR_ERR(ctx->reset_gpio);
+	}
+	ret = gpiod_direction_output(ctx->reset_gpio, 1);
+	if (ret < 0) {
+		dev_err(dev, "cannot configure reset-gpios %d\n", ret);
+		return ret;
+	}
+
+	ctx->lcd_en_gpio = devm_gpiod_get(dev, "lcd-en");
+	if (IS_ERR(ctx->lcd_en_gpio)) {
+		dev_err(dev, "cannot get reset-gpios %ld\n",
+			PTR_ERR(ctx->lcd_en_gpio));
+		return PTR_ERR(ctx->lcd_en_gpio);
+	}
+	ret = gpiod_direction_output(ctx->lcd_en_gpio, 1);
+	if (ret < 0) {
+		dev_err(dev, "cannot configure reset-gpios %d\n", ret);
+		return ret;
+	}
+
+	drm_panel_init(&ctx->panel);
+	ctx->panel.dev = dev;
+	ctx->panel.funcs = &s6e3ha2_drm_funcs;
+
+	ret = drm_panel_add(&ctx->panel);
+	if (ret < 0)
+		return ret;
+
+	ret = mipi_dsi_attach(dsi);
+	if (ret < 0)
+		drm_panel_remove(&ctx->panel);
+
+	return ret;
+}
+
+static int s6e3ha2_remove(struct mipi_dsi_device *dsi)
+{
+	struct s6e3ha2 *ctx = mipi_dsi_get_drvdata(dsi);
+
+	mipi_dsi_detach(dsi);
+	drm_panel_remove(&ctx->panel);
+
+	return 0;
+}
+
+static struct of_device_id s6e3ha2_of_match[] = {
+	{ .compatible = "samsung,s6e3ha2" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, s6e3ha2_of_match);
+
+static struct mipi_dsi_driver s6e3ha2_driver = {
+	.probe = s6e3ha2_probe,
+	.remove = s6e3ha2_remove,
+	.driver = {
+		.name = "panel_s6e3ha2",
+		.owner = THIS_MODULE,
+		.of_match_table = s6e3ha2_of_match,
+	},
+};
+module_mipi_dsi_driver(s6e3ha2_driver);
+
+MODULE_AUTHOR("Donghwa Lee <dh09.lee@samsung.com>");
+MODULE_AUTHOR("Hyungwon Hwang <human.hwang@samsung.com>");
+MODULE_DESCRIPTION("MIPI-DSI based s6e3ha2 AMOLED LCD Panel Driver");
+MODULE_LICENSE("GPL v2");