| Message ID | 1424261968-9392-1-git-send-email-deathsimple@vodafone.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, Feb 18, 2015 at 7:19 AM, Christian König <deathsimple@vodafone.de> wrote: > From: Leo Liu <leo.liu@amd.com> > > v2: disable it on suspend > > Signed-off-by: Christian König <christian.koenig@amd.com> Applied the whole series to my tree. Thanks! Alex > --- > drivers/gpu/drm/radeon/cik.c | 8 ++++++++ > drivers/gpu/drm/radeon/cikd.h | 4 ++++ > 2 files changed, 12 insertions(+) > > diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c > index e6a4ba2..0c993da 100644 > --- a/drivers/gpu/drm/radeon/cik.c > +++ b/drivers/gpu/drm/radeon/cik.c > @@ -3613,6 +3613,8 @@ static void cik_gpu_init(struct radeon_device *rdev) > } > > WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); > + WREG32(SRBM_INT_CNTL, 0x1); > + WREG32(SRBM_INT_ACK, 0x1); > > WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN); > > @@ -7230,6 +7232,8 @@ static void cik_disable_interrupt_state(struct radeon_device *rdev) > WREG32(CP_ME2_PIPE3_INT_CNTL, 0); > /* grbm */ > WREG32(GRBM_INT_CNTL, 0); > + /* SRBM */ > + WREG32(SRBM_INT_CNTL, 0); > /* vline/vblank, etc. */ > WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); > WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); > @@ -8046,6 +8050,10 @@ restart_ih: > break; > } > break; > + case 96: > + DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR)); > + WREG32(SRBM_INT_ACK, 0x1); > + break; > case 124: /* UVD */ > DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data); > radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX); > diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h > index 03003f8..c648e19 100644 > --- a/drivers/gpu/drm/radeon/cikd.h > +++ b/drivers/gpu/drm/radeon/cikd.h > @@ -482,6 +482,10 @@ > #define SOFT_RESET_ORB (1 << 23) > #define SOFT_RESET_VCE (1 << 24) > > +#define SRBM_READ_ERROR 0xE98 > +#define SRBM_INT_CNTL 0xEA0 > +#define SRBM_INT_ACK 0xEA8 > + > #define VM_L2_CNTL 0x1400 > #define ENABLE_L2_CACHE (1 << 0) > #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) > -- > 1.9.1 > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/dri-devel
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index e6a4ba2..0c993da 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c @@ -3613,6 +3613,8 @@ static void cik_gpu_init(struct radeon_device *rdev) } WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); + WREG32(SRBM_INT_CNTL, 0x1); + WREG32(SRBM_INT_ACK, 0x1); WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN); @@ -7230,6 +7232,8 @@ static void cik_disable_interrupt_state(struct radeon_device *rdev) WREG32(CP_ME2_PIPE3_INT_CNTL, 0); /* grbm */ WREG32(GRBM_INT_CNTL, 0); + /* SRBM */ + WREG32(SRBM_INT_CNTL, 0); /* vline/vblank, etc. */ WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); @@ -8046,6 +8050,10 @@ restart_ih: break; } break; + case 96: + DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR)); + WREG32(SRBM_INT_ACK, 0x1); + break; case 124: /* UVD */ DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data); radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX); diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h index 03003f8..c648e19 100644 --- a/drivers/gpu/drm/radeon/cikd.h +++ b/drivers/gpu/drm/radeon/cikd.h @@ -482,6 +482,10 @@ #define SOFT_RESET_ORB (1 << 23) #define SOFT_RESET_VCE (1 << 24) +#define SRBM_READ_ERROR 0xE98 +#define SRBM_INT_CNTL 0xEA0 +#define SRBM_INT_ACK 0xEA8 + #define VM_L2_CNTL 0x1400 #define ENABLE_L2_CACHE (1 << 0) #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)