From patchwork Thu Mar 5 16:20:10 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Lespiau, Damien" X-Patchwork-Id: 5947431 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 60F409F373 for ; Thu, 5 Mar 2015 16:20:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7EF59202E9 for ; Thu, 5 Mar 2015 16:20:31 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 8996B20381 for ; Thu, 5 Mar 2015 16:20:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 107C96E7F9; Thu, 5 Mar 2015 08:20:27 -0800 (PST) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 5EE746E7F6; Thu, 5 Mar 2015 08:20:25 -0800 (PST) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP; 05 Mar 2015 08:20:25 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.11,347,1422950400"; d="scan'208";a="462980594" Received: from rmoore5-mobl1.amr.corp.intel.com (HELO strange.ger.corp.intel.com) ([10.252.11.84]) by FMSMGA003.fm.intel.com with ESMTP; 05 Mar 2015 08:14:02 -0800 From: Damien Lespiau To: intel-gfx@lists.freedesktop.org Subject: [PATCH 02/12] intel: Introduce an drm_intel_device object Date: Thu, 5 Mar 2015 16:20:10 +0000 Message-Id: <1425572420-10067-3-git-send-email-damien.lespiau@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1425572420-10067-1-git-send-email-damien.lespiau@intel.com> References: <1425572420-10067-1-git-send-email-damien.lespiau@intel.com> MIME-Version: 1.0 Cc: dri-devel@lists.freedesktop.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The intention here is to: - have a single object that represents a device - reuse the kernel i915_pciids.h file so we only one place to update and copy the file over. - hide the various information about an intel device in that object instead of having endless #define in intel_chipset.h. That can be basic info like which gen are we talking about or, hopefully soon, detailed information about the device (number of slices/sub-slices/eus/...) We'll start slowy by making this API an internal detail at the moment. Maybe it can grow into something better. Signed-off-by: Damien Lespiau --- intel/Makefile.sources | 3 + intel/i915_pciids.h | 289 +++++++++++++++++++++++++++++++++++++++++++++++ intel/intel_device.c | 300 +++++++++++++++++++++++++++++++++++++++++++++++++ intel/intel_device.h | 99 ++++++++++++++++ 4 files changed, 691 insertions(+) create mode 100644 intel/i915_pciids.h create mode 100644 intel/intel_device.c create mode 100644 intel/intel_device.h diff --git a/intel/Makefile.sources b/intel/Makefile.sources index 7b2272c..0077a17 100644 --- a/intel/Makefile.sources +++ b/intel/Makefile.sources @@ -1,9 +1,12 @@ LIBDRM_INTEL_FILES := \ + i915_pciids.h \ intel_bufmgr.c \ intel_bufmgr_priv.h \ intel_bufmgr_fake.c \ intel_bufmgr_gem.c \ intel_decode.c \ + intel_device.c \ + intel_device.h \ intel_chipset.h \ mm.c \ mm.h diff --git a/intel/i915_pciids.h b/intel/i915_pciids.h new file mode 100644 index 0000000..f2e47fd --- /dev/null +++ b/intel/i915_pciids.h @@ -0,0 +1,289 @@ +/* + * Copyright 2013 Intel Corporation + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef _I915_PCIIDS_H +#define _I915_PCIIDS_H + +/* + * A pci_device_id struct { + * __u32 vendor, device; + * __u32 subvendor, subdevice; + * __u32 class, class_mask; + * kernel_ulong_t driver_data; + * }; + * Don't use C99 here because "class" is reserved and we want to + * give userspace flexibility. + */ +#define INTEL_VGA_DEVICE(id, info) { \ + 0x8086, id, \ + ~0, ~0, \ + 0x030000, 0xff0000, \ + (unsigned long) info } + +#define INTEL_QUANTA_VGA_DEVICE(info) { \ + 0x8086, 0x16a, \ + 0x152d, 0x8990, \ + 0x030000, 0xff0000, \ + (unsigned long) info } + +#define INTEL_I830_IDS(info) \ + INTEL_VGA_DEVICE(0x3577, info) + +#define INTEL_I845G_IDS(info) \ + INTEL_VGA_DEVICE(0x2562, info) + +#define INTEL_I85X_IDS(info) \ + INTEL_VGA_DEVICE(0x3582, info), /* I855_GM */ \ + INTEL_VGA_DEVICE(0x358e, info) + +#define INTEL_I865G_IDS(info) \ + INTEL_VGA_DEVICE(0x2572, info) /* I865_G */ + +#define INTEL_I915G_IDS(info) \ + INTEL_VGA_DEVICE(0x2582, info), /* I915_G */ \ + INTEL_VGA_DEVICE(0x258a, info) /* E7221_G */ + +#define INTEL_I915GM_IDS(info) \ + INTEL_VGA_DEVICE(0x2592, info) /* I915_GM */ + +#define INTEL_I945G_IDS(info) \ + INTEL_VGA_DEVICE(0x2772, info) /* I945_G */ + +#define INTEL_I945GM_IDS(info) \ + INTEL_VGA_DEVICE(0x27a2, info), /* I945_GM */ \ + INTEL_VGA_DEVICE(0x27ae, info) /* I945_GME */ + +#define INTEL_I965G_IDS(info) \ + INTEL_VGA_DEVICE(0x2972, info), /* I946_GZ */ \ + INTEL_VGA_DEVICE(0x2982, info), /* G35_G */ \ + INTEL_VGA_DEVICE(0x2992, info), /* I965_Q */ \ + INTEL_VGA_DEVICE(0x29a2, info) /* I965_G */ + +#define INTEL_G33_IDS(info) \ + INTEL_VGA_DEVICE(0x29b2, info), /* Q35_G */ \ + INTEL_VGA_DEVICE(0x29c2, info), /* G33_G */ \ + INTEL_VGA_DEVICE(0x29d2, info) /* Q33_G */ + +#define INTEL_I965GM_IDS(info) \ + INTEL_VGA_DEVICE(0x2a02, info), /* I965_GM */ \ + INTEL_VGA_DEVICE(0x2a12, info) /* I965_GME */ + +#define INTEL_GM45_IDS(info) \ + INTEL_VGA_DEVICE(0x2a42, info) /* GM45_G */ + +#define INTEL_G45_IDS(info) \ + INTEL_VGA_DEVICE(0x2e02, info), /* IGD_E_G */ \ + INTEL_VGA_DEVICE(0x2e12, info), /* Q45_G */ \ + INTEL_VGA_DEVICE(0x2e22, info), /* G45_G */ \ + INTEL_VGA_DEVICE(0x2e32, info), /* G41_G */ \ + INTEL_VGA_DEVICE(0x2e42, info), /* B43_G */ \ + INTEL_VGA_DEVICE(0x2e92, info) /* B43_G.1 */ + +#define INTEL_PINEVIEW_IDS(info) \ + INTEL_VGA_DEVICE(0xa001, info), \ + INTEL_VGA_DEVICE(0xa011, info) + +#define INTEL_IRONLAKE_D_IDS(info) \ + INTEL_VGA_DEVICE(0x0042, info) + +#define INTEL_IRONLAKE_M_IDS(info) \ + INTEL_VGA_DEVICE(0x0046, info) + +#define INTEL_SNB_D_IDS(info) \ + INTEL_VGA_DEVICE(0x0102, info), \ + INTEL_VGA_DEVICE(0x0112, info), \ + INTEL_VGA_DEVICE(0x0122, info), \ + INTEL_VGA_DEVICE(0x010A, info) + +#define INTEL_SNB_M_IDS(info) \ + INTEL_VGA_DEVICE(0x0106, info), \ + INTEL_VGA_DEVICE(0x0116, info), \ + INTEL_VGA_DEVICE(0x0126, info) + +#define INTEL_IVB_M_IDS(info) \ + INTEL_VGA_DEVICE(0x0156, info), /* GT1 mobile */ \ + INTEL_VGA_DEVICE(0x0166, info) /* GT2 mobile */ + +#define INTEL_IVB_D_IDS(info) \ + INTEL_VGA_DEVICE(0x0152, info), /* GT1 desktop */ \ + INTEL_VGA_DEVICE(0x0162, info), /* GT2 desktop */ \ + INTEL_VGA_DEVICE(0x015a, info), /* GT1 server */ \ + INTEL_VGA_DEVICE(0x016a, info) /* GT2 server */ + +#define INTEL_IVB_Q_IDS(info) \ + INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */ + +#define INTEL_HSW_D_IDS(info) \ + INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \ + INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \ + INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \ + INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \ + INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \ + INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \ + INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \ + INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \ + INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \ + INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \ + INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \ + INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \ + INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \ + INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \ + INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \ + INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \ + INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \ + INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \ + INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \ + INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \ + INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \ + INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \ + INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \ + INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \ + INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \ + INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \ + INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \ + INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \ + INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \ + INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \ + INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \ + INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \ + INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \ + INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \ + INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \ + INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \ + INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \ + INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \ + INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \ + INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \ + INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \ + INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \ + INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \ + INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \ + INTEL_VGA_DEVICE(0x0D2E, info) /* CRW GT3 reserved */ \ + +#define INTEL_HSW_M_IDS(info) \ + INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \ + INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \ + INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \ + INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \ + INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \ + INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \ + INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \ + INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \ + INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \ + INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \ + INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \ + INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \ + INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \ + INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \ + INTEL_VGA_DEVICE(0x0D26, info) /* CRW GT3 mobile */ + +#define INTEL_VLV_M_IDS(info) \ + INTEL_VGA_DEVICE(0x0f30, info), \ + INTEL_VGA_DEVICE(0x0f31, info), \ + INTEL_VGA_DEVICE(0x0f32, info), \ + INTEL_VGA_DEVICE(0x0f33, info), \ + INTEL_VGA_DEVICE(0x0157, info) + +#define INTEL_VLV_D_IDS(info) \ + INTEL_VGA_DEVICE(0x0155, info) + +#define _INTEL_BDW_M(gt, id, info) \ + INTEL_VGA_DEVICE((((gt) - 1) << 4) | (id), info) +#define _INTEL_BDW_D(gt, id, info) \ + INTEL_VGA_DEVICE((((gt) - 1) << 4) | (id), info) + +#define _INTEL_BDW_M_IDS(gt, info) \ + _INTEL_BDW_M(gt, 0x1602, info), /* Halo */ \ + _INTEL_BDW_M(gt, 0x1606, info), /* ULT */ \ + _INTEL_BDW_M(gt, 0x160B, info), /* ULT */ \ + _INTEL_BDW_M(gt, 0x160E, info) /* ULX */ + +#define _INTEL_BDW_D_IDS(gt, info) \ + _INTEL_BDW_D(gt, 0x160A, info), /* Server */ \ + _INTEL_BDW_D(gt, 0x160D, info) /* Workstation */ + +#define INTEL_BDW_GT12M_IDS(info) \ + _INTEL_BDW_M_IDS(1, info), \ + _INTEL_BDW_M_IDS(2, info) + +#define INTEL_BDW_GT12D_IDS(info) \ + _INTEL_BDW_D_IDS(1, info), \ + _INTEL_BDW_D_IDS(2, info) + +#define INTEL_BDW_GT3M_IDS(info) \ + _INTEL_BDW_M_IDS(3, info) + +#define INTEL_BDW_GT3D_IDS(info) \ + _INTEL_BDW_D_IDS(3, info) + +#define INTEL_BDW_RSVDM_IDS(info) \ + _INTEL_BDW_M_IDS(4, info) + +#define INTEL_BDW_RSVDD_IDS(info) \ + _INTEL_BDW_D_IDS(4, info) + +#define INTEL_BDW_M_IDS(info) \ + INTEL_BDW_GT12M_IDS(info), \ + INTEL_BDW_GT3M_IDS(info), \ + INTEL_BDW_RSVDM_IDS(info) + +#define INTEL_BDW_D_IDS(info) \ + INTEL_BDW_GT12D_IDS(info), \ + INTEL_BDW_GT3D_IDS(info), \ + INTEL_BDW_RSVDD_IDS(info) + +#define INTEL_CHV_IDS(info) \ + INTEL_VGA_DEVICE(0x22b0, info), \ + INTEL_VGA_DEVICE(0x22b1, info), \ + INTEL_VGA_DEVICE(0x22b2, info), \ + INTEL_VGA_DEVICE(0x22b3, info) + +#define INTEL_SKL_GT1_IDS(info) \ + INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \ + INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \ + INTEL_VGA_DEVICE(0x1902, info), /* DT GT1 */ \ + INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \ + INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */ + +#define INTEL_SKL_GT2_IDS(info) \ + INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \ + INTEL_VGA_DEVICE(0x1921, info), /* ULT GT2F */ \ + INTEL_VGA_DEVICE(0x191E, info), /* ULX GT2 */ \ + INTEL_VGA_DEVICE(0x1912, info), /* DT GT2 */ \ + INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \ + INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \ + INTEL_VGA_DEVICE(0x191D, info) /* WKS GT2 */ + +#define INTEL_SKL_GT3_IDS(info) \ + INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3 */ \ + INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \ + INTEL_VGA_DEVICE(0x192A, info) /* SRV GT3 */ \ + +#define INTEL_SKL_IDS(info) \ + INTEL_SKL_GT1_IDS(info), \ + INTEL_SKL_GT2_IDS(info), \ + INTEL_SKL_GT3_IDS(info) + + +#endif /* _I915_PCIIDS_H */ diff --git a/intel/intel_device.c b/intel/intel_device.c new file mode 100644 index 0000000..92f498c --- /dev/null +++ b/intel/intel_device.c @@ -0,0 +1,300 @@ +/* + * Copyright © 2014 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include +#include +#include +#include + +#include + +#include "i915_drm.h" +#include "i915_pciids.h" +#include "intel_device.h" + +#ifdef HAVE_VALGRIND +#include +#include +#define VG(x) x +#else +#define VG(x) +#endif + +#define VG_CLEAR(s) VG(memset(&s, 0, sizeof(s))) + +#define DBG(...) do { \ + if (bufmgr_gem->bufmgr.debug) \ + fprintf(stderr, __VA_ARGS__); \ +} while (0) + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#endif + +/* + * The first few fields here have to match the layout of the publicly defined + * struct drm_intel_device + */ +struct drm_intel_device_info { + uint16_t chip, gen; +}; + +struct _drm_intel_device { + struct drm_intel_device_info info; + int fd; + uint16_t devid; +}; + +#define _to_dev(d) ((struct _drm_intel_device *)(d)) + +static const struct drm_intel_device_info intel_i830_info = { + .chip = DRM_INTEL_CHIP_I830, + .gen = 2, +}; +static const struct drm_intel_device_info intel_i845_info = { + .chip = DRM_INTEL_CHIP_I845, + .gen = 2, +}; +static const struct drm_intel_device_info intel_i85x_info = { + .chip = DRM_INTEL_CHIP_I85X, + .gen = 2, +}; +static const struct drm_intel_device_info intel_i865_info = { + .chip = DRM_INTEL_CHIP_I865, + .gen = 2, +}; + +static const struct drm_intel_device_info intel_i915_info = { + .chip = DRM_INTEL_CHIP_I915, + .gen = 3, +}; +static const struct drm_intel_device_info intel_i945_info = { + .chip = DRM_INTEL_CHIP_I945, + .gen = 3, +}; + +static const struct drm_intel_device_info intel_g33_info = { + .chip = DRM_INTEL_CHIP_G33, + .gen = 3, +}; +static const struct drm_intel_device_info intel_pineview_info = { + .chip = DRM_INTEL_CHIP_PINEVIEW, + .gen = 3, +}; + +static const struct drm_intel_device_info intel_i965_info = { + .chip = DRM_INTEL_CHIP_I965, + .gen = 4, +}; + +static const struct drm_intel_device_info intel_g4x_info = { + .chip = DRM_INTEL_CHIP_IG4X, + .gen = 4, +}; + +static const struct drm_intel_device_info intel_ironlake_info = { + .chip = DRM_INTEL_CHIP_IRONLAKE, + .gen = 5, +}; + +static const struct drm_intel_device_info intel_sandybridge_info = { + .chip = DRM_INTEL_CHIP_SANDYBRIDGE, + .gen = 6, +}; + +static const struct drm_intel_device_info intel_ivybridge_info = { + .chip = DRM_INTEL_CHIP_IVYBRIDGE, + .gen = 7, +}; +static const struct drm_intel_device_info intel_valleyview_info = { + .chip = DRM_INTEL_CHIP_VALLEYVIEW, + .gen = 7, +}; + +static const struct drm_intel_device_info intel_haswell_info = { + .chip = DRM_INTEL_CHIP_HASWELL, + .gen = 7, +}; + +static const struct drm_intel_device_info intel_broadwell_info = { + .chip = DRM_INTEL_CHIP_BROADWELL, + .gen = 8, +}; + +static const struct drm_intel_device_info intel_cherryview_info = { + .chip = DRM_INTEL_CHIP_CHERRYVIEW, + .gen = 8, +}; + +static const struct drm_intel_device_info intel_skylake_info = { + .chip = DRM_INTEL_CHIP_SKYLAKE, + .gen = 9, +}; + +/* + * let's not introduce a dependency on libpciaccess just for the struct + * pci_id_match definition... + */ +struct device_info_match { + uint32_t vendor, device; + uint32_t subvendor, subdevice; + uint32_t class, class_mask; + unsigned long info; +}; + +static const struct device_info_match intel_devices[] = { + INTEL_I830_IDS(&intel_i830_info), + INTEL_I845G_IDS(&intel_i830_info), + INTEL_I85X_IDS(&intel_i85x_info), + INTEL_I865G_IDS(&intel_i865_info), + + INTEL_I915G_IDS(&intel_i915_info), + INTEL_I915GM_IDS(&intel_i915_info), + INTEL_I945G_IDS(&intel_i945_info), + INTEL_I945GM_IDS(&intel_i945_info), + + INTEL_G33_IDS(&intel_g33_info), + INTEL_PINEVIEW_IDS(&intel_pineview_info), + + INTEL_I965G_IDS(&intel_i965_info), + INTEL_I965GM_IDS(&intel_i965_info), + + INTEL_G45_IDS(&intel_g4x_info), + INTEL_GM45_IDS(&intel_g4x_info), + + INTEL_IRONLAKE_D_IDS(&intel_ironlake_info), + INTEL_IRONLAKE_M_IDS(&intel_ironlake_info), + + INTEL_SNB_D_IDS(&intel_sandybridge_info), + INTEL_SNB_M_IDS(&intel_sandybridge_info), + + INTEL_IVB_D_IDS(&intel_ivybridge_info), + INTEL_IVB_M_IDS(&intel_ivybridge_info), + + INTEL_HSW_D_IDS(&intel_haswell_info), + INTEL_HSW_M_IDS(&intel_haswell_info), + + INTEL_VLV_D_IDS(&intel_valleyview_info), + INTEL_VLV_M_IDS(&intel_valleyview_info), + + INTEL_BDW_D_IDS(&intel_broadwell_info), + INTEL_BDW_M_IDS(&intel_broadwell_info), + + INTEL_CHV_IDS(&intel_cherryview_info), + + INTEL_SKL_IDS(&intel_skylake_info), +}; + +static struct drm_intel_device * +_drm_intel_device_populate_info(struct _drm_intel_device *_dev) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(intel_devices); i++) { + const struct device_info_match *entry = &intel_devices[i]; + + if (_dev->devid != entry->device) + continue; + + _dev->info = *(struct drm_intel_device_info *)entry->info; + return (struct drm_intel_device *)_dev; + } + + free(_dev); + return NULL; +} + +struct drm_intel_device *drm_intel_device_new_from_devid(uint16_t devid) +{ + struct _drm_intel_device *_dev; + + _dev = calloc(1, sizeof(*_dev)); + if (_dev == NULL) + return NULL; + + _dev->fd = -1; + _dev->devid = devid; + + return _drm_intel_device_populate_info(_dev); +} + +/** + * Get the PCI ID for the device from the opened DRM fd. This can be overridden + * by setting the INTEL_DEVID_OVERRIDE environment variable to the desired ID. + */ +static uint16_t _drm_intel_device_get_devid(struct _drm_intel_device *_dev) +{ + int devid; + struct drm_i915_getparam gp; + int ret; + + if (geteuid() == getuid()) { + char *devid_override; + + devid_override = getenv("INTEL_DEVID_OVERRIDE"); + if (devid_override) { + _dev->fd = -1; + return strtod(devid_override, NULL); + } + } + + VG_CLEAR(devid); + VG_CLEAR(gp); + gp.param = I915_PARAM_CHIPSET_ID; + gp.value = &devid; + ret = drmIoctl(_dev->fd, DRM_IOCTL_I915_GETPARAM, &gp); + if (ret) + return 0; + + return devid; +} + +struct drm_intel_device *drm_intel_device_new(int fd) +{ + struct _drm_intel_device *_dev; + + _dev = calloc(1, sizeof(*_dev)); + if (_dev == NULL) + return NULL; + + _dev->fd = fd; + _dev->devid = _drm_intel_device_get_devid(_dev); + + return _drm_intel_device_populate_info(_dev); +} + +void drm_intel_device_free(struct drm_intel_device *dev) +{ + free(dev); +} + +uint16_t drm_intel_device_get_devid(struct drm_intel_device *dev) +{ + struct _drm_intel_device *_dev = _to_dev(dev); + + return _dev->devid; +} diff --git a/intel/intel_device.h b/intel/intel_device.h new file mode 100644 index 0000000..513e09a --- /dev/null +++ b/intel/intel_device.h @@ -0,0 +1,99 @@ +/* + * Copyright © 2014 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#ifndef __INTEL_DEVICE_H__ +#define __INTEL_DEVICE_H__ + +#include +#include + +/* This is not an exhaustive list, but enough for our purposes */ +enum drm_intel_chip { + + /* gen 2 */ + DRM_INTEL_CHIP_I830, + DRM_INTEL_CHIP_I845, + DRM_INTEL_CHIP_I85X, + DRM_INTEL_CHIP_I865, + + /* gen 3 */ + DRM_INTEL_CHIP_I915, + DRM_INTEL_CHIP_I945, + DRM_INTEL_CHIP_G33, + DRM_INTEL_CHIP_PINEVIEW, + + /* gen 4 */ + DRM_INTEL_CHIP_I965, + DRM_INTEL_CHIP_IG4X, + + /* gen 5 */ + DRM_INTEL_CHIP_IRONLAKE, + + /* gen 6 */ + DRM_INTEL_CHIP_SANDYBRIDGE, + + /* gen 7 */ + DRM_INTEL_CHIP_IVYBRIDGE, + DRM_INTEL_CHIP_HASWELL, + DRM_INTEL_CHIP_VALLEYVIEW, + + /* gen 8 */ + DRM_INTEL_CHIP_BROADWELL, + DRM_INTEL_CHIP_CHERRYVIEW, + + /* gen 9 */ + DRM_INTEL_CHIP_SKYLAKE, +}; + +/* + * Note that this structure definition doesn't actually hold the internal + * fields of the real struct drm_intel_device device allocated by + * drm_intel_device_init(). This is to allow direct access to widely used + * fields like ->gen without having to go through a function call. + * + * This means that this structure shouldn't statically or stack allocated. + */ +struct drm_intel_device { + uint16_t chip, gen; +}; + +/* + * Allocate a drm_intel_device object from: + * - a PCI devid or, + * - an opened DRM file descriptor + * + * The version taking a fd is the preferred one as it allows run-time support + * from the kernel. + * + * The returned object has to be freed with drm_intel_device_free(). When being + * instantiated with a file descriptor, the object does not take ownership of + * the fd and so _free() will not close that fd. + */ +struct drm_intel_device *drm_intel_device_new(int fd); +struct drm_intel_device *drm_intel_device_new_from_devid(uint16_t devid); +void drm_intel_device_free(struct drm_intel_device *dev); + +/* Retrieve the PCI device id */ +uint16_t drm_intel_device_get_devid(struct drm_intel_device *dev); + +#endif /* __INTEL_DEVICE_H__ */