From patchwork Wed Mar 25 08:59:39 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomeu Vizoso X-Patchwork-Id: 6096321 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id AF1FFBF910 for ; Thu, 26 Mar 2015 02:10:19 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1B7E520389 for ; Thu, 26 Mar 2015 02:10:17 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 98CDB20251 for ; Thu, 26 Mar 2015 02:10:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6600E6E970; Wed, 25 Mar 2015 19:10:14 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wi0-f177.google.com (mail-wi0-f177.google.com [209.85.212.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 192946E804 for ; Wed, 25 Mar 2015 02:00:36 -0700 (PDT) Received: by wixw10 with SMTP id w10so28501105wix.0 for ; Wed, 25 Mar 2015 02:00:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=n1VvrLEpOC40v227oAwK0Wri1z4B5WPUmQIT8ZKMDTk=; b=R8SeG8OuHb4sD7YPDHPSFUkjSpvBeYrVXUvdW+9eHX7/y+Se2sCWRdK7NcaERGcHiX 5OZ/ntBwO1eNIsJVBmmz79v9PaQgmd5dyDKmk9z9gdQuOzt1/liSQuPKXbEp3ADUyTeD tUPL3bU/jNanum4SIeiIp6Hyo7BCykpDWVjmwVtS6+KDLbm4BUtWwl5m40tJ6hlstxdP u8+4aPxMaenMD141eLQV6S0ui1N3bhYCSxw8duPS414IHBeHVYQMeGU2wVYCI/cB/TTB K4/ztgZR+OgTRx04PbNP/FBWFIBbv9aSjDld3uKy/DIoOl9dyrlvtDqxkxjPRUTvHe6k Jqcg== X-Received: by 10.194.59.199 with SMTP id b7mr16346572wjr.26.1427274035240; Wed, 25 Mar 2015 02:00:35 -0700 (PDT) Received: from cizrna.lan ([109.72.12.28]) by mx.google.com with ESMTPSA id bx3sm2646538wjc.21.2015.03.25.02.00.33 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 25 Mar 2015 02:00:34 -0700 (PDT) From: Tomeu Vizoso To: linux-tegra@vger.kernel.org Subject: [PATCH] drm/tegra: Reset the SOR during initialization Date: Wed, 25 Mar 2015 09:59:39 +0100 Message-Id: <1427273979-394-1-git-send-email-tomeu.vizoso@collabora.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <20150324102447.GA18115@ulmo.nvidia.com> References: <20150324102447.GA18115@ulmo.nvidia.com> X-Mailman-Approved-At: Wed, 25 Mar 2015 19:09:46 -0700 Cc: Alexandre Courbot , =?UTF-8?q?Terje=20Bergstr=C3=B6m?= , Tomeu Vizoso , Stephen Warren , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP As there isn't a way for the firmware on the Nyan chromebooks to hand over the display to the kernel, and the kernel isn't redoing the whole configuration at present. With this patch, the SOR is brought to a known state and we get correct display on every boot. Signed-off-by: Tomeu Vizoso --- v7: * Move the reset to the host1x_client_ops.init callback as suggested by Thierry * Reduced the time during which the reset line is asserted from 20ms to 2ms --- drivers/gpu/drm/tegra/sor.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index 2afe478..027a25d22 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -1354,12 +1354,30 @@ static int tegra_sor_init(struct host1x_client *client) } } + /* + * XXX: Remove this reset once proper hand-over from firmware to + * kernel is possible. + */ + err = reset_control_assert(sor->rst); + if (err < 0) { + dev_err(sor->dev, "failed to assert SOR reset: %d\n", err); + return err; + } + err = clk_prepare_enable(sor->clk); if (err < 0) { dev_err(sor->dev, "failed to enable clock: %d\n", err); return err; } + msleep(2); + + err = reset_control_deassert(sor->rst); + if (err < 0) { + dev_err(sor->dev, "failed to deassert SOR reset: %d\n", err); + return err; + } + err = clk_prepare_enable(sor->clk_safe); if (err < 0) return err;