From patchwork Mon Mar 30 08:33:03 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomeu Vizoso X-Patchwork-Id: 6127131 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 5EC3CBF4A7 for ; Tue, 31 Mar 2015 02:25:42 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 867F220459 for ; Tue, 31 Mar 2015 02:25:41 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 8E2A120458 for ; Tue, 31 Mar 2015 02:25:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E8AC46E351; Mon, 30 Mar 2015 19:25:32 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wi0-f176.google.com (mail-wi0-f176.google.com [209.85.212.176]) by gabe.freedesktop.org (Postfix) with ESMTP id 81F4E6E339 for ; Mon, 30 Mar 2015 01:33:50 -0700 (PDT) Received: by wibgn9 with SMTP id gn9so117846826wib.1 for ; Mon, 30 Mar 2015 01:33:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id; bh=R5YDpM2YSjmyOBNe/So2nXK0X52VTOH18ESX9Owl0xM=; b=xZqu97GP0+KgUZ61aA5aPzTZel5UIGZ8ZEZq4dtg3/mZnKxNfqJBvBBPsB0XwtqenP lVxutLpNuoZ2MYddIutI3imWWww0aw2Z5HuNuD07O/WcB9GDLRtaKz1sk8Yi9619GOS2 V+0MR517uZGkZKsnYSYWdvCQFJ2kF9nUiOu1Ep//+Y9C/+oJgfS3gMQhvd5EHENUpT5W ypCZRLO0/Nyk1xvlzuL5hZmDQvLxT/XN/zrR2+kIHtK248/xb99W1jXzZIhGSAkkyjGo 41o1U7Sp4PZDgBne442DlM/k2nnqtc3StqRYjiXxoxhPOXySli0XCVLLcsnlfFvbHa8d 7v7A== X-Received: by 10.194.192.167 with SMTP id hh7mr61765603wjc.151.1427704429746; Mon, 30 Mar 2015 01:33:49 -0700 (PDT) Received: from cizrna.lan ([109.72.12.90]) by mx.google.com with ESMTPSA id nh17sm14655139wic.5.2015.03.30.01.33.47 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 30 Mar 2015 01:33:48 -0700 (PDT) From: Tomeu Vizoso To: linux-tegra@vger.kernel.org Subject: [PATCH v8] drm/tegra: Reset the SOR during initialization Date: Mon, 30 Mar 2015 10:33:03 +0200 Message-Id: <1427704383-23780-1-git-send-email-tomeu.vizoso@collabora.com> X-Mailer: git-send-email 2.1.0 X-Mailman-Approved-At: Mon, 30 Mar 2015 19:25:31 -0700 Cc: Alexandre Courbot , =?UTF-8?q?Terje=20Bergstr=C3=B6m?= , Tomeu Vizoso , Stephen Warren , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP As there isn't a way for the firmware on the Nyan chromebooks to hand over the display to the kernel, and the kernel isn't redoing the whole configuration at present. With this patch, the SOR is brought to a known state and we get correct display on every boot. Signed-off-by: Tomeu Vizoso --- v8: * Use usleep_range instead of msleep as suggested by Dmitry Osipenko v7: * Move the reset to the host1x_client_ops.init callback as suggested by Thierry * Reduced the time during which the reset line is asserted from 20ms to 2ms --- drivers/gpu/drm/tegra/sor.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index 2afe478..dc51a8e 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -1354,12 +1354,30 @@ static int tegra_sor_init(struct host1x_client *client) } } + /* + * XXX: Remove this reset once proper hand-over from firmware to + * kernel is possible. + */ + err = reset_control_assert(sor->rst); + if (err < 0) { + dev_err(sor->dev, "failed to assert SOR reset: %d\n", err); + return err; + } + err = clk_prepare_enable(sor->clk); if (err < 0) { dev_err(sor->dev, "failed to enable clock: %d\n", err); return err; } + usleep_range(1000, 3000); + + err = reset_control_deassert(sor->rst); + if (err < 0) { + dev_err(sor->dev, "failed to deassert SOR reset: %d\n", err); + return err; + } + err = clk_prepare_enable(sor->clk_safe); if (err < 0) return err;