@@ -135,7 +135,7 @@ static void etnaviv_buffer_dump(struct etnaviv_gpu *gpu,
u32 size = obj->base.size;
u32 *ptr = obj->vaddr + off;
- dev_info(gpu->drm->dev, "virt %p phys 0x%08x free 0x%08x\n",
+ dev_info(gpu->dev, "virt %p phys 0x%08x free 0x%08x\n",
ptr, obj->paddr + off, size - len * 4 - off);
print_hex_dump(KERN_INFO, "cmd ", DUMP_PREFIX_OFFSET, 16, 4,
@@ -126,8 +126,7 @@ static void load_gpu(struct drm_device *dev)
etnaviv_gpu_pm_resume(g);
ret = etnaviv_gpu_init(g);
if (ret) {
- dev_err(dev->dev, "%s hw init failed: %d\n",
- g->name, ret);
+ dev_err(g->dev, "hw init failed: %d\n", ret);
priv->gpu[i] = NULL;
}
}
@@ -206,7 +205,7 @@ static int etnaviv_gpu_show(struct drm_device *dev, struct seq_file *m)
for (i = 0; i < ETNA_MAX_PIPES; i++) {
gpu = priv->gpu[i];
if (gpu) {
- seq_printf(m, "%s Status:\n", gpu->name);
+ seq_printf(m, "%s Status:\n", dev_name(gpu->dev));
etnaviv_gpu_debugfs(gpu, m);
}
}
@@ -223,7 +222,8 @@ static int etnaviv_gem_show(struct drm_device *dev, struct seq_file *m)
for (i = 0; i < ETNA_MAX_PIPES; i++) {
gpu = priv->gpu[i];
if (gpu) {
- seq_printf(m, "Active Objects (%s):\n", gpu->name);
+ seq_printf(m, "Active Objects (%s):\n",
+ dev_name(gpu->dev));
msm_gem_describe_objects(&gpu->active_list, m);
}
}
@@ -104,7 +104,7 @@ int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, uint32_t param,
break;
default:
- DBG("%s: invalid param: %u", gpu->name, param);
+ DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
return -EINVAL;
}
@@ -157,7 +157,7 @@ static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
gpu->identity.vertex_output_buffer_size =
1 << gpu->identity.vertex_output_buffer_size;
} else {
- dev_err(gpu->drm->dev, "TODO: determine GPU specs based on model\n");
+ dev_err(gpu->dev, "TODO: determine GPU specs based on model\n");
}
switch (gpu->identity.instruction_count) {
@@ -178,25 +178,25 @@ static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
break;
}
- dev_info(gpu->drm->dev, "stream_count: %x\n",
+ dev_info(gpu->dev, "stream_count: %x\n",
gpu->identity.stream_count);
- dev_info(gpu->drm->dev, "register_max: %x\n",
+ dev_info(gpu->dev, "register_max: %x\n",
gpu->identity.register_max);
- dev_info(gpu->drm->dev, "thread_count: %x\n",
+ dev_info(gpu->dev, "thread_count: %x\n",
gpu->identity.thread_count);
- dev_info(gpu->drm->dev, "vertex_cache_size: %x\n",
+ dev_info(gpu->dev, "vertex_cache_size: %x\n",
gpu->identity.vertex_cache_size);
- dev_info(gpu->drm->dev, "shader_core_count: %x\n",
+ dev_info(gpu->dev, "shader_core_count: %x\n",
gpu->identity.shader_core_count);
- dev_info(gpu->drm->dev, "pixel_pipes: %x\n",
+ dev_info(gpu->dev, "pixel_pipes: %x\n",
gpu->identity.pixel_pipes);
- dev_info(gpu->drm->dev, "vertex_output_buffer_size: %x\n",
+ dev_info(gpu->dev, "vertex_output_buffer_size: %x\n",
gpu->identity.vertex_output_buffer_size);
- dev_info(gpu->drm->dev, "buffer_size: %x\n",
+ dev_info(gpu->dev, "buffer_size: %x\n",
gpu->identity.buffer_size);
- dev_info(gpu->drm->dev, "instruction_count: %x\n",
+ dev_info(gpu->dev, "instruction_count: %x\n",
gpu->identity.instruction_count);
- dev_info(gpu->drm->dev, "num_constants: %x\n",
+ dev_info(gpu->dev, "num_constants: %x\n",
gpu->identity.num_constants);
}
@@ -242,8 +242,8 @@ static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
}
}
- dev_info(gpu->drm->dev, "model: %x\n", gpu->identity.model);
- dev_info(gpu->drm->dev, "revision: %x\n", gpu->identity.revision);
+ dev_info(gpu->dev, "model: %x\n", gpu->identity.model);
+ dev_info(gpu->dev, "revision: %x\n", gpu->identity.revision);
gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE);
@@ -275,13 +275,13 @@ static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3);
}
- dev_info(gpu->drm->dev, "minor_features: %x\n",
+ dev_info(gpu->dev, "minor_features: %x\n",
gpu->identity.minor_features0);
- dev_info(gpu->drm->dev, "minor_features1: %x\n",
+ dev_info(gpu->dev, "minor_features1: %x\n",
gpu->identity.minor_features1);
- dev_info(gpu->drm->dev, "minor_features2: %x\n",
+ dev_info(gpu->dev, "minor_features2: %x\n",
gpu->identity.minor_features2);
- dev_info(gpu->drm->dev, "minor_features3: %x\n",
+ dev_info(gpu->dev, "minor_features3: %x\n",
gpu->identity.minor_features3);
etnaviv_hw_specs(gpu);
@@ -334,8 +334,7 @@ static void etnaviv_hw_reset(struct etnaviv_gpu *gpu)
/* try reseting again if FE it not idle */
if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) {
- dev_dbg(gpu->drm->dev, "%s: FE is not idle\n",
- gpu->name);
+ dev_dbg(gpu->dev, "FE is not idle\n");
continue;
}
@@ -345,8 +344,7 @@ static void etnaviv_hw_reset(struct etnaviv_gpu *gpu)
/* is the GPU idle? */
if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0)
|| ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) {
- dev_dbg(gpu->drm->dev, "%s: GPU is not idle\n",
- gpu->name);
+ dev_dbg(gpu->dev, "GPU is not idle\n");
continue;
}
@@ -385,7 +383,7 @@ int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
* simple and to get something working, just use a single address space:
*/
mmuv2 = gpu->identity.minor_features1 & chipMinorFeatures1_MMU_VERSION;
- dev_dbg(gpu->drm->dev, "mmuv2: %d\n", mmuv2);
+ dev_dbg(gpu->dev, "mmuv2: %d\n", mmuv2);
if (!mmuv2) {
iommu = etnaviv_iommu_domain_alloc(gpu);
@@ -414,7 +412,7 @@ int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
if (IS_ERR(gpu->buffer)) {
ret = PTR_ERR(gpu->buffer);
gpu->buffer = NULL;
- dev_err(gpu->drm->dev, "could not create buffer: %d\n", ret);
+ dev_err(gpu->dev, "could not create buffer: %d\n", ret);
goto fail;
}
@@ -622,7 +620,7 @@ int etnaviv_gpu_pm_resume(struct etnaviv_gpu *gpu)
{
int ret;
- DBG("%s", gpu->name);
+ DBG("%s", dev_name(gpu->dev));
ret = enable_pwrrail(gpu);
if (ret)
@@ -643,7 +641,7 @@ int etnaviv_gpu_pm_suspend(struct etnaviv_gpu *gpu)
{
int ret;
- DBG("%s", gpu->name);
+ DBG("%s", dev_name(gpu->dev));
ret = disable_axi(gpu);
if (ret)
@@ -669,7 +667,7 @@ static void recover_worker(struct work_struct *work)
recover_work);
struct drm_device *dev = gpu->drm;
- dev_err(dev->dev, "%s: hangcheck recover!\n", gpu->name);
+ dev_err(gpu->dev, "hangcheck recover!\n");
mutex_lock(&dev->struct_mutex);
/* TODO gpu->funcs->recover(gpu); */
@@ -680,7 +678,7 @@ static void recover_worker(struct work_struct *work)
static void hangcheck_timer_reset(struct etnaviv_gpu *gpu)
{
- DBG("%s", gpu->name);
+ DBG("%s", dev_name(gpu->dev));
mod_timer(&gpu->hangcheck_timer,
round_jiffies_up(jiffies + DRM_MSM_HANGCHECK_JIFFIES));
}
@@ -698,12 +696,10 @@ static void hangcheck_handler(unsigned long data)
} else if (fence_after(gpu->submitted_fence, fence)) {
/* no progress and not done.. hung! */
gpu->hangcheck_fence = fence;
- dev_err(dev->dev, "%s: hangcheck detected gpu lockup!\n",
- gpu->name);
- dev_err(dev->dev, "%s: completed fence: %u\n",
- gpu->name, fence);
- dev_err(dev->dev, "%s: submitted fence: %u\n",
- gpu->name, gpu->submitted_fence);
+ dev_err(gpu->dev, "hangcheck detected gpu lockup!\n");
+ dev_err(gpu->dev, " completed fence: %u\n", fence);
+ dev_err(gpu->dev, " submitted fence: %u\n",
+ gpu->submitted_fence);
queue_work(priv->wq, &gpu->recover_work);
}
@@ -724,7 +720,7 @@ static unsigned int event_alloc(struct etnaviv_gpu *gpu)
ret = wait_for_completion_timeout(&gpu->event_free,
msecs_to_jiffies(10 * 10000));
if (!ret)
- dev_err(gpu->drm->dev, "wait_for_completion_timeout failed");
+ dev_err(gpu->dev, "wait_for_completion_timeout failed");
spin_lock_irqsave(&gpu->event_spinlock, flags);
@@ -749,7 +745,7 @@ static void event_free(struct etnaviv_gpu *gpu, unsigned int event)
spin_lock_irqsave(&gpu->event_spinlock, flags);
if (gpu->event[event].used == false) {
- dev_warn(gpu->drm->dev, "event %u is already marked as free",
+ dev_warn(gpu->dev, "event %u is already marked as free",
event);
spin_unlock_irqrestore(&gpu->event_spinlock, flags);
} else {
@@ -878,14 +874,14 @@ static irqreturn_t irq_handler(int irq, void *data)
u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE);
if (intr != 0) {
- dev_dbg(gpu->drm->dev, "intr 0x%08x\n", intr);
+ dev_dbg(gpu->dev, "intr 0x%08x\n", intr);
if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR)
- dev_err(gpu->drm->dev, "AXI bus error\n");
+ dev_err(gpu->dev, "AXI bus error\n");
else {
uint8_t event = __fls(intr);
- dev_dbg(gpu->drm->dev, "event %u\n", event);
+ dev_dbg(gpu->dev, "event %u\n", event);
gpu->retired_fence = gpu->event[event].fence;
gpu->last_ring_pos = gpu->event[event].ring_pos;
event_free(gpu, event);
@@ -938,7 +934,7 @@ static void etnaviv_gpu_unbind(struct device *dev, struct device *master,
del_timer(&gpu->hangcheck_timer);
- DBG("%s", gpu->name);
+ DBG("%s", dev_name(gpu->dev));
WARN_ON(!list_empty(&gpu->active_list));
@@ -985,10 +981,10 @@ static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
if (!match)
return -EINVAL;
- gpu->name = pdev->name;
+ gpu->dev = &pdev->dev;
/* Map registers: */
- gpu->mmio = etnaviv_ioremap(pdev, NULL, gpu->name);
+ gpu->mmio = etnaviv_ioremap(pdev, NULL, dev_name(gpu->dev));
if (IS_ERR(gpu->mmio))
return PTR_ERR(gpu->mmio);
@@ -1001,7 +997,7 @@ static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
}
err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler,
- IRQF_TRIGGER_HIGH, gpu->name, gpu);
+ IRQF_TRIGGER_HIGH, dev_name(gpu->dev), gpu);
if (err) {
dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err);
goto fail;
@@ -85,8 +85,8 @@ struct etnaviv_event {
};
struct etnaviv_gpu {
- const char *name;
struct drm_device *drm;
+ struct device *dev;
struct etnaviv_chip_identity identity;
int pipe;