From patchwork Fri Apr 10 05:55:22 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hyungwon Hwang X-Patchwork-Id: 6191721 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id D9A14BF4A6 for ; Fri, 10 Apr 2015 05:55:50 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DEBC9203A0 for ; Fri, 10 Apr 2015 05:55:49 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 6A43320375 for ; Fri, 10 Apr 2015 05:55:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DE0416E890; Thu, 9 Apr 2015 22:55:39 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mailout2.samsung.com (mailout2.samsung.com [203.254.224.25]) by gabe.freedesktop.org (Postfix) with ESMTP id 978EF6E88E for ; Thu, 9 Apr 2015 22:55:37 -0700 (PDT) Received: from epcpsbgr5.samsung.com (u145.gpu120.samsung.co.kr [203.254.230.145]) by mailout2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NMK008CSTSOI830@mailout2.samsung.com> for dri-devel@lists.freedesktop.org; Fri, 10 Apr 2015 14:55:36 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.113]) by epcpsbgr5.samsung.com (EPCPMTA) with SMTP id F2.0E.17770.8D567255; Fri, 10 Apr 2015 14:55:36 +0900 (KST) X-AuditID: cbfee691-f79ca6d00000456a-bb-552765d833c8 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id CD.D3.25346.7D567255; Fri, 10 Apr 2015 14:55:36 +0900 (KST) Received: from localhost.localdomain ([10.252.82.145]) by mmp1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NMK00MM0TSKKM40@mmp1.samsung.com>; Fri, 10 Apr 2015 14:55:35 +0900 (KST) From: Hyungwon Hwang To: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, inki.dae@samsung.com, daniel@fooishbar.org Subject: [PATCH v5 04/12] drm/exynos: dsi: rename pll_clk to sclk_clk Date: Fri, 10 Apr 2015 14:55:22 +0900 Message-id: <1428645330-1043-5-git-send-email-human.hwang@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1428645330-1043-1-git-send-email-human.hwang@samsung.com> References: <1428645330-1043-1-git-send-email-human.hwang@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrPLMWRmVeSWpSXmKPExsWyRsSkUPdGqnqowewuHovrX56zWlxpnc5q Mf/IOVaL6+ftLK58fc9msXRGH6vFpPsTWCxe3LvIYjFj8ks2B06PF1+3MXvc7z7O5NG3ZRWj x+dNcgEsUVw2Kak5mWWpRfp2CVwZ666+ZC+Yp1zx4uE/pgbG3zJdjJwcEgImEufaT7BB2GIS F+6tB7K5OIQEljJKTH2xiAWm6PyznUwQiUWMErsnT4Sq+sEo8aZvLxNIFZuAnsSCaz/YQWwR gVyJ/hcvwDqYBXoYJRqvTAYbJSzgKvHq/wagIg4OFgFViYtHwOp5BdwklmzdzQixTU7i5LHJ rCAlnALuEke3poKEhYBKPu7ZxgoyUkJgEbvEhgefwc5mERCQ+Db5EAtIvYSArMSmA8wQYyQl Dq64wTKBUXgBI8MqRtHUguSC4qT0IlO94sTc4tK8dL3k/NxNjMBwP/3v2cQdjPcPWB9iFOBg VOLhbYhVDxViTSwrrsw9xGgKtGEis5Rocj4wqvJK4g2NzYwsTE1MjY3MLc2UxHl1pH8GCwmk J5akZqemFqQWxReV5qQWH2Jk4uCUamDUPizKon+19yjvp4d33gqb+AVyCuw7cy/0WsVf9XjV C5I/HAPi1vGURb1giA5OuhYvz5K8dLrpIZPTEu/fPprqMMtnjeNd0+US6RHSW8qDP5WnyG66 +G/fS01J2ROvv/yz/brtkGfnxnX7s1iYHNqvbt/DqRJVZxsvkGHckDBxxuk00z8/gp4rsRRn JBpqMRcVJwIAIGxA73ICAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrJIsWRmVeSWpSXmKPExsVy+t9jAd0bqeqhBjNPMFpc//Kc1eJK63RW i/lHzrFaXD9vZ3Hl63s2i6Uz+lgtJt2fwGLx4t5FFosZk1+yOXB6vPi6jdnjfvdxJo++LasY PT5vkgtgiWpgtMlITUxJLVJIzUvOT8nMS7dV8g6Od443NTMw1DW0tDBXUshLzE21VXLxCdB1 y8wBukVJoSwxpxQoFJBYXKykb4dpQmiIm64FTGOErm9IEFyPkQEaSFjDmLHu6kv2gnnKFS8e /mNqYPwt08XIySEhYCJx/tlOJghbTOLCvfVsXYxcHEICixgldk+eCOX8YJR407cXrIpNQE9i wbUf7CC2iECuRP+LF0wgRcwCPYwSjVcms4AkhAVcJV793wBUxMHBIqAqcfEIWD2vgJvEkq27 GSG2yUmcPDaZFaSEU8Bd4ujWVJCwEFDJxz3bWCcw8i5gZFjFKJpakFxQnJSea6hXnJhbXJqX rpecn7uJERxNz6R2MK5ssDjEKMDBqMTDeyNePVSINbGsuDL3EKMEB7OSCG9lLFCINyWxsiq1 KD++qDQntfgQoynQTROZpUST84GRnlcSb2hsYmZkaWRuaGFkbK4kzjtHVy5USCA9sSQ1OzW1 ILUIpo+Jg1OqgdHEq2big0UXms/feOFs/TCEy31FyoafXatOsW+NZClb+NKh/u6fFNW9QUaL Xk2eHHK7P/6HX+PKiKT3Fcy5cXt0v22dpWd27ZHP1/AHd5aaGO6wYZ14Ps/guGXu2U+pJ3qu Gu5rL2QRjNyfMUeAZ33mmTX7pBICb/mfdpN9pf0zdpoK4/67nu+UWIozEg21mIuKEwEPtukr vAIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Cc: dh09.lee@samsung.com, sw0312.kim@samsung.com, Hyungwon Hwang , cw00.choi@samsung.com X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch renames pll_clk to sclk_clk. The clock referenced by pll_clk is actually not the pll input clock for dsi. The pll input clock comes from the board's oscillator directly. Signed-off-by: Hyungwon Hwang --- Changes for v3: - Newly added Changes for v4: - None Changes for v5: - None .../devicetree/bindings/video/exynos_dsim.txt | 7 ++--- drivers/gpu/drm/exynos/exynos_drm_dsi.c | 31 ++++++++-------------- 2 files changed, 15 insertions(+), 23 deletions(-) diff --git a/Documentation/devicetree/bindings/video/exynos_dsim.txt b/Documentation/devicetree/bindings/video/exynos_dsim.txt index 802aa7e..44659dd 100644 --- a/Documentation/devicetree/bindings/video/exynos_dsim.txt +++ b/Documentation/devicetree/bindings/video/exynos_dsim.txt @@ -10,13 +10,14 @@ Required properties: - interrupts: should contain DSI interrupt - clocks: list of clock specifiers, must contain an entry for each required entry in clock-names - - clock-names: should include "bus_clk"and "pll_clk" entries + - clock-names: should include "bus_clk"and "sclk_mipi" entries + the use of "pll_clk" is deprecated - phys: list of phy specifiers, must contain an entry for each required entry in phy-names - phy-names: should include "dsim" entry - vddcore-supply: MIPI DSIM Core voltage supply (e.g. 1.1V) - vddio-supply: MIPI DSIM I/O and PLL voltage supply (e.g. 1.8V) - - samsung,pll-clock-frequency: specifies frequency of the "pll_clk" clock + - samsung,pll-clock-frequency: specifies frequency of the oscillator clock - #address-cells, #size-cells: should be set respectively to <1> and <0> according to DSI host bindings (see MIPI DSI bindings [1]) @@ -48,7 +49,7 @@ Example: reg = <0x11C80000 0x10000>; interrupts = <0 79 0>; clocks = <&clock 286>, <&clock 143>; - clock-names = "bus_clk", "pll_clk"; + clock-names = "bus_clk", "sclk_mipi"; phys = <&mipi_phy 1>; phy-names = "dsim"; vddcore-supply = <&vusb_reg>; diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index 0492715..178be44 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -277,7 +277,7 @@ struct exynos_dsi { void __iomem *reg_base; struct phy *phy; - struct clk *pll_clk; + struct clk *sclk_clk; struct clk *bus_clk; struct regulator_bulk_data supplies[2]; int irq; @@ -431,16 +431,7 @@ static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi, u16 m; u32 reg; - clk_set_rate(dsi->pll_clk, dsi->pll_clk_rate); - - fin = clk_get_rate(dsi->pll_clk); - if (!fin) { - dev_err(dsi->dev, "failed to get PLL clock frequency\n"); - return 0; - } - - dev_dbg(dsi->dev, "PLL input frequency: %lu\n", fin); - + fin = dsi->pll_clk_rate; fout = exynos_dsi_pll_find_pms(dsi, fin, freq, &p, &m, &s); if (!fout) { dev_err(dsi->dev, @@ -1308,10 +1299,10 @@ static int exynos_dsi_poweron(struct exynos_dsi *dsi) goto err_bus_clk; } - ret = clk_prepare_enable(dsi->pll_clk); + ret = clk_prepare_enable(dsi->sclk_clk); if (ret < 0) { dev_err(dsi->dev, "cannot enable pll clock %d\n", ret); - goto err_pll_clk; + goto err_sclk_clk; } ret = phy_power_on(dsi->phy); @@ -1323,8 +1314,8 @@ static int exynos_dsi_poweron(struct exynos_dsi *dsi) return 0; err_phy: - clk_disable_unprepare(dsi->pll_clk); -err_pll_clk: + clk_disable_unprepare(dsi->sclk_clk); +err_sclk_clk: clk_disable_unprepare(dsi->bus_clk); err_bus_clk: regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); @@ -1350,7 +1341,7 @@ static void exynos_dsi_poweroff(struct exynos_dsi *dsi) phy_power_off(dsi->phy); - clk_disable_unprepare(dsi->pll_clk); + clk_disable_unprepare(dsi->sclk_clk); clk_disable_unprepare(dsi->bus_clk); ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); @@ -1713,10 +1704,10 @@ static int exynos_dsi_probe(struct platform_device *pdev) return -EPROBE_DEFER; } - dsi->pll_clk = devm_clk_get(dev, "pll_clk"); - if (IS_ERR(dsi->pll_clk)) { - dev_info(dev, "failed to get dsi pll input clock\n"); - ret = PTR_ERR(dsi->pll_clk); + dsi->sclk_clk = devm_clk_get(dev, "sclk_mipi"); + if (IS_ERR(dsi->sclk_clk)) { + dev_info(dev, "failed to get dsi sclk clock\n"); + ret = PTR_ERR(dsi->sclk_clk); goto err_del_component; }