From patchwork Mon May 11 01:38:26 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Zhang X-Patchwork-Id: 6372721 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 175AABEEE1 for ; Mon, 11 May 2015 02:51:39 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B6EB6203EB for ; Mon, 11 May 2015 02:51:36 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id AE3B6203E3 for ; Mon, 11 May 2015 02:51:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BF95D6E15C; Sun, 10 May 2015 19:51:31 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from hqemgate16.nvidia.com (hqemgate16.nvidia.com [216.228.121.65]) by gabe.freedesktop.org (Postfix) with ESMTP id 211EA6E13A for ; Sun, 10 May 2015 18:38:42 -0700 (PDT) Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Sun, 10 May 2015 18:38:38 -0700 Received: from hqemhub02.nvidia.com ([172.20.150.31]) by hqnvupgp07.nvidia.com (PGP Universal service); Sun, 10 May 2015 18:37:04 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Sun, 10 May 2015 18:37:04 -0700 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server id 8.3.342.0; Sun, 10 May 2015 18:38:41 -0700 Received: from markz-hp6200.nvidia.com (Not Verified[10.19.224.127]) by hqnvemgw01.nvidia.com with MailMarshal (v7,1,2,5326) id ; Sun, 10 May 2015 18:38:41 -0700 From: Mark Zhang To: thierry.reding@gmail.com Subject: [RFC PATCH 07/12] drm/tegra: Set NC(Non-contiguous) mode to dc for one-shot Date: Mon, 11 May 2015 09:38:26 +0800 Message-ID: <1431308311-4470-8-git-send-email-markz@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1431308311-4470-1-git-send-email-markz@nvidia.com> References: <1431308311-4470-1-git-send-email-markz@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-Mailman-Approved-At: Sun, 10 May 2015 19:51:31 -0700 Cc: linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP If dc is about to work in one-shot mode, we need to set dc's scan mode to NC(Non-contiguous). There are 2 things which can make dc send frame again: - TE signal is received - Driver sets the NC_HOST_TRIG_ENABLE Signed-off-by: Mark Zhang --- drivers/gpu/drm/tegra/dc.c | 43 +++++++++++++++++++++++++++++-------------- drivers/gpu/drm/tegra/dc.h | 5 +++++ 2 files changed, 34 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index a287e4fec865..b88c29322c6f 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -1248,10 +1248,26 @@ static void tegra_crtc_mode_set_nofb(struct drm_crtc *crtc) tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL); } - value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); - value &= ~DISP_CTRL_MODE_MASK; - value |= DISP_CTRL_MODE_C_DISPLAY; - tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); + if (mode->flags & DRM_MODE_FLAG_PREFER_ONE_SHOT) { + /* enable MSF & set MSF polarity */ + value = MSF_ENABLE | MSF_LSPI; + if (mode->flags & DRM_MODE_FLAG_TE_POLARITY_HIGH) + value |= MSF_POLARITY_HIGH; + else + value |= MSF_POLARITY_LOW; + tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND_OPTION0); + + /* set non-continuous mode */ + value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); + value &= ~DISP_CTRL_MODE_MASK; + value |= DISP_CTRL_MODE_NC_DISPLAY; + tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); + } else { + value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); + value &= ~DISP_CTRL_MODE_MASK; + value |= DISP_CTRL_MODE_C_DISPLAY; + tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); + } value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | @@ -1319,16 +1335,11 @@ static irqreturn_t tegra_dc_irq(int irq, void *data) status = tegra_dc_readl(dc, DC_CMD_INT_STATUS); tegra_dc_writel(dc, status, DC_CMD_INT_STATUS); - if (status & FRAME_END_INT) { - /* - dev_dbg(dc->dev, "%s(): frame end\n", __func__); - */ - } + if (status & FRAME_END_INT) + dev_info(dc->dev, "%s(): frame end\n", __func__); if (status & VBLANK_INT) { - /* - dev_dbg(dc->dev, "%s(): vertical blank\n", __func__); - */ + dev_info(dc->dev, "%s(): vertical blank\n", __func__); drm_crtc_handle_vblank(&dc->base); tegra_dc_finish_page_flip(dc); } @@ -1339,6 +1350,9 @@ static irqreturn_t tegra_dc_irq(int irq, void *data) */ } + if (status & MSF_INT) + dev_info(dc->dev, "MSF_INT received.\n"); + return IRQ_HANDLED; } @@ -1732,10 +1746,11 @@ static int tegra_dc_init(struct host1x_client *client) WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1); tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); - value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT; + value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | + WIN_C_UF_INT | MSF_INT; tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); - value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT; + value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | MSF_INT; tegra_dc_writel(dc, value, DC_CMD_INT_MASK); if (dc->soc->supports_border_color) diff --git a/drivers/gpu/drm/tegra/dc.h b/drivers/gpu/drm/tegra/dc.h index 55792daabbb5..4a2d0fec5853 100644 --- a/drivers/gpu/drm/tegra/dc.h +++ b/drivers/gpu/drm/tegra/dc.h @@ -27,6 +27,10 @@ #define DC_CMD_CONT_SYNCPT_VSYNC 0x028 #define SYNCPT_VSYNC_ENABLE (1 << 8) #define DC_CMD_DISPLAY_COMMAND_OPTION0 0x031 +#define MSF_ENABLE (1 << 1) +#define MSF_LSPI (0 << 2) +#define MSF_POLARITY_HIGH (0 << 0) +#define MSF_POLARITY_LOW (1 << 0) #define DC_CMD_DISPLAY_COMMAND 0x032 #define DISP_CTRL_MODE_STOP (0 << 5) #define DISP_CTRL_MODE_C_DISPLAY (1 << 5) @@ -53,6 +57,7 @@ #define WIN_A_UF_INT (1 << 8) #define WIN_B_UF_INT (1 << 9) #define WIN_C_UF_INT (1 << 10) +#define MSF_INT (1 << 12) #define WIN_A_OF_INT (1 << 14) #define WIN_B_OF_INT (1 << 15) #define WIN_C_OF_INT (1 << 16)