diff --git a/tests/tegra/Makefile.am b/tests/tegra/Makefile.am
index 8e625c8fedb8..e3ef60e42039 100644
--- a/tests/tegra/Makefile.am
+++ b/tests/tegra/Makefile.am
@@ -10,4 +10,5 @@ LDADD = \
 	../../libdrm.la
 
 noinst_PROGRAMS = \
-	openclose
+	openclose \
+	submit_vic
diff --git a/tests/tegra/host1x.h b/tests/tegra/host1x.h
new file mode 100644
index 000000000000..9a72c8e69f85
--- /dev/null
+++ b/tests/tegra/host1x.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright © 2015 NVIDIA Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef HOST1X_H
+#define HOST1X_H
+
+#include <stdint.h>
+
+enum host1x_class {
+	HOST1X_CLASS_HOST1X = 0x1,
+	HOST1X_CLASS_GR2D = 0x51,
+	HOST1X_CLASS_GR2D_SB = 0x52,
+	HOST1X_CLASS_VIC = 0x5D,
+	HOST1X_CLASS_GR3D = 0x60,
+};
+
+static inline uint32_t host1x_opcode_setclass(
+	unsigned class_id, unsigned offset, unsigned mask)
+{
+	return (0 << 28) | (offset << 16) | (class_id << 6) | mask;
+}
+
+static inline uint32_t host1x_opcode_incr(unsigned offset, unsigned count)
+{
+	return (1 << 28) | (offset << 16) | count;
+}
+
+static inline uint32_t host1x_opcode_nonincr(unsigned offset, unsigned count)
+{
+	return (2 << 28) | (offset << 16) | count;
+}
+
+#endif
diff --git a/tests/tegra/submit_vic.c b/tests/tegra/submit_vic.c
new file mode 100644
index 000000000000..472fde93a528
--- /dev/null
+++ b/tests/tegra/submit_vic.c
@@ -0,0 +1,315 @@
+/*
+ * Copyright © 2015 NVIDIA Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#  include "config.h"
+#endif
+
+#include <stdio.h>
+#include <fcntl.h>
+#include <string.h>
+#include <unistd.h>
+#include <sys/ioctl.h>
+#include <sys/mman.h>
+
+#include <tegra_drm.h>
+
+#include "host1x.h"
+#include "vic.h"
+#include "xf86drm.h"
+#include "tegra.h"
+
+static const char default_device[] = "/dev/dri/card0";
+
+int main(int argc, char *argv[])
+{
+	struct drm_tegra_get_syncpt get_syncpt_args;
+	struct drm_tegra_bo *cmdbuf_bo, *histbuf_bo, *outbuf_bo,
+		*configbuf_bo;
+	uint32_t cmdbuf_bo_handle, histbuf_bo_handle,
+		outbuf_bo_handle, configbuf_bo_handle;
+	struct drm_tegra_open_channel open_channel_args = {0};
+	struct drm_tegra_syncpt submit_syncpt_incr = {0};
+	struct drm_tegra_cmdbuf submit_cmdbuf = {0};
+	struct drm_tegra_submit submit_args = {0};
+	struct drm_tegra_reloc submit_relocs[3];
+	struct drm_tegra_syncpt_wait wait_args = {0};
+	ConfigStruct *config_struct;
+	struct drm_tegra *tegra;
+	drmVersionPtr version;
+	const char *device;
+	uint32_t *cmdbuf;
+	uint32_t *outbuf;
+	uint32_t i, j;
+	void *histbuf;
+	int err, fd;
+
+	if (argc < 2)
+		device = default_device;
+	else
+		device = argv[1];
+
+	fd = open(device, O_RDWR);
+	if (fd < 0) {
+		printf("Failed to open device %s\n", device);
+		return fd;
+	}
+
+	version = drmGetVersion(fd);
+	if (version) {
+		printf("Version: %d.%d.%d\n", version->version_major,
+		       version->version_minor, version->version_patchlevel);
+		printf("  Name: %s\n", version->name);
+		printf("  Date: %s\n", version->date);
+		printf("  Description: %s\n", version->desc);
+
+		drmFreeVersion(version);
+	}
+
+	err = drm_tegra_new(&tegra, fd);
+	if (err < 0) {
+		printf("Failed to open Tegra DRM device (%d)\n", err);
+		return err;
+	}
+
+	/* open channel */
+	open_channel_args.client = HOST1X_CLASS_VIC;
+	err = drmIoctl(fd, DRM_IOCTL_TEGRA_OPEN_CHANNEL, &open_channel_args);
+	if (err) {
+		printf("Failed to open channel (%d)\n", err);
+		return err;
+	}
+
+	/* allocate cmdbuf */
+	err = drm_tegra_bo_new(&cmdbuf_bo, tegra, 0, 4096);
+	if (err) {
+		printf("Failed to create cmdbuf (%d)\n", err);
+		return err;
+	}
+
+	/* get command buffer handle */
+	err = drm_tegra_bo_get_handle(cmdbuf_bo, &cmdbuf_bo_handle);
+	if (err) {
+		printf("Failed to get cmdbuf handle (%d)\n", err);
+		return err;
+	}
+
+	/* map cmdbuf */
+	err = drm_tegra_bo_map(cmdbuf_bo, (void **)&cmdbuf);
+	if (err) {
+		printf("Failed to mmap cmdbuf (%d)\n", err);
+		return err;
+	}
+
+	/* create the config struct buffer */
+	err = drm_tegra_bo_new(&configbuf_bo, tegra, 0, sizeof(ConfigStruct));
+	if (err) {
+		printf("Failed to create config struct (%d)\n", err);
+		return err;
+	}
+
+	/* get command buffer handle */
+	err = drm_tegra_bo_get_handle(configbuf_bo, &configbuf_bo_handle);
+	if (err) {
+		printf("Failed to get cmdbuf handle (%d)\n", err);
+		return err;
+	}
+
+	/* get offset for the config struct buffer */
+	err = drm_tegra_bo_map(configbuf_bo, (void **)&config_struct);
+	if (err) {
+		printf("Failed to mmap config struct (%d)\n", err);
+		return err;
+	}
+
+	/* allocate the hist buffer */
+	err = drm_tegra_bo_new(&histbuf_bo, tegra, 0, 4096);
+	if (err) {
+		printf("Failed to create histbuf (%d)\n", err);
+		return err;
+	}
+
+	/* get command buffer handle */
+	err = drm_tegra_bo_get_handle(histbuf_bo, &histbuf_bo_handle);
+	if (err) {
+		printf("Failed to get histbuf handle (%d)\n", err);
+		return err;
+	}
+
+	/* get offset for the hist buffer */
+	err = drm_tegra_bo_map(histbuf_bo, (void **)&histbuf);
+	if (err) {
+		printf("Failed to mmap histbuf (%d)\n", err);
+		return err;
+	}
+
+	/* allocate the output surface */
+	err = drm_tegra_bo_new(&outbuf_bo, tegra, 0, 32 * 1024);
+	if (err) {
+		printf("Failed to create outbuf (%d)\n", err);
+		return err;
+	}
+
+	/* get command buffer handle */
+	err = drm_tegra_bo_get_handle(outbuf_bo, &outbuf_bo_handle);
+	if (err) {
+		printf("Failed to get outbuf handle (%d)\n", err);
+		return err;
+	}
+
+	/* get the offset for the outbuf */
+	err = drm_tegra_bo_map(outbuf_bo, (void **)&outbuf);
+	if (err) {
+		printf("Failed to mmap outbuf (%d)\n", err);
+		return err;
+	}
+
+	/* get channel syncpoint */
+	get_syncpt_args.context = open_channel_args.context;
+	get_syncpt_args.index = 0;
+	err = drmIoctl(fd, DRM_IOCTL_TEGRA_GET_SYNCPT, &get_syncpt_args);
+	if (err) {
+		printf("Failed to get syncpoint (%d)\n", err);
+		return err;
+	}
+
+	memset(histbuf, 0, 4096);
+
+	memset(config_struct, 0, sizeof(*config_struct));
+	config_struct->surfaceList0Struct.TargetRectRight = 199;
+	config_struct->surfaceList0Struct.TargetRectBottom = 31;
+	config_struct->blending0Struct.PixelFormat = 34; /* R8G8B8A8 */
+	config_struct->blending0Struct.BackgroundAlpha = 1023;
+	config_struct->blending0Struct.BackgroundR = 0;
+	config_struct->blending0Struct.BackgroundG = 1023;
+	config_struct->blending0Struct.BackgroundB = 0;
+	config_struct->blending0Struct.LumaWidth = 255;
+	config_struct->blending0Struct.LumaHeight = 31;
+	config_struct->blending0Struct.ChromaWidth = 16383;
+	config_struct->blending0Struct.ChromaHeight = 16383;
+	config_struct->blending0Struct.TargetRectRight = 199;
+	config_struct->blending0Struct.TargetRectBottom = 31;
+	config_struct->blending0Struct.SurfaceWidth = 199;
+	config_struct->blending0Struct.SurfaceHeight = 31;
+	config_struct->fetchControl0Struct.TargetRectRight = 199;
+	config_struct->fetchControl0Struct.TargetRectBottom = 31;
+
+	i = 0;
+	cmdbuf[i++] = host1x_opcode_setclass(HOST1X_CLASS_VIC, 0, 0);
+
+	/* setup size of config_struct */
+	cmdbuf[i++] = host1x_opcode_incr(VIC_UCLASS_METHOD_OFFSET, 2);
+	cmdbuf[i++] = NVA0B6_VIDEO_COMPOSITOR_SET_CONTROL_PARAMS >> 2;
+	cmdbuf[i++] = (sizeof(*config_struct) / 16) << 16;
+
+	/* set configuration buffer offset */
+	cmdbuf[i++] = host1x_opcode_incr(VIC_UCLASS_METHOD_OFFSET, 2);
+	cmdbuf[i++] = NVA0B6_VIDEO_COMPOSITOR_SET_CONFIG_STRUCT_OFFSET >> 2;
+	submit_relocs[0].cmdbuf.handle = cmdbuf_bo_handle;
+	submit_relocs[0].cmdbuf.offset = i * 4;
+	submit_relocs[0].target.handle = configbuf_bo_handle;
+	submit_relocs[0].target.offset = 0;
+	submit_relocs[0].shift = 8;
+	submit_relocs[0].pad = 0;
+	cmdbuf[i++] = 0xdeadbeef;
+
+	/* set history buffer offset */
+	cmdbuf[i++] = host1x_opcode_incr(VIC_UCLASS_METHOD_OFFSET, 2);
+	cmdbuf[i++] = NVA0B6_VIDEO_COMPOSITOR_SET_HIST_OFFSET >> 2;
+	submit_relocs[1].cmdbuf.handle = cmdbuf_bo_handle;
+	submit_relocs[1].cmdbuf.offset = i * 4;
+	submit_relocs[1].target.handle = histbuf_bo_handle;
+	submit_relocs[1].target.offset = 0;
+	submit_relocs[1].shift = 8;
+	submit_relocs[1].pad = 0;
+	cmdbuf[i++] = 0xdeadbeef;
+
+	/* set output buffer */
+	cmdbuf[i++] = host1x_opcode_incr(VIC_UCLASS_METHOD_OFFSET, 2);
+	cmdbuf[i++] = NVA0B6_VIDEO_COMPOSITOR_SET_OUTPUT_SURFACE_LUMA_OFFSET >> 2;
+	submit_relocs[2].cmdbuf.handle = cmdbuf_bo_handle;
+	submit_relocs[2].cmdbuf.offset = i * 4;
+	submit_relocs[2].target.handle = outbuf_bo_handle;
+	submit_relocs[2].target.offset = 0;
+	submit_relocs[2].shift = 8;
+	submit_relocs[2].pad = 0;
+	cmdbuf[i++] = 0xdeadbeef;
+
+	/* execute */
+	cmdbuf[i++] = host1x_opcode_incr(VIC_UCLASS_METHOD_OFFSET, 2);
+	cmdbuf[i++] = NVA0B6_VIDEO_COMPOSITOR_EXECUTE >> 2;
+	cmdbuf[i++] = 1 << 8;
+
+	/* increment syncpoint */
+	cmdbuf[i++] = host1x_opcode_nonincr(0, 1);
+	cmdbuf[i++] = get_syncpt_args.id | 1 << 8;
+
+	/* initialize submit: we make a single syncpoint increment */
+	submit_syncpt_incr.id = get_syncpt_args.id;
+	submit_syncpt_incr.incrs = 1;
+
+	/* ..and we have a single command buffer */
+	submit_cmdbuf.handle = cmdbuf_bo_handle;
+	submit_cmdbuf.offset = 0;
+	submit_cmdbuf.words = i;
+
+	/* make the submit */
+	submit_args.context = open_channel_args.context;
+	submit_args.num_syncpts = 1;
+	submit_args.num_cmdbufs = 1;
+	submit_args.num_relocs = 3;
+	submit_args.syncpts = (uintptr_t)&submit_syncpt_incr;
+	submit_args.cmdbufs = (uintptr_t)&submit_cmdbuf;
+	submit_args.relocs = (uintptr_t)&submit_relocs;
+
+	err = drmIoctl(fd, DRM_IOCTL_TEGRA_SUBMIT, &submit_args);
+	if (err) {
+		printf("Failed to submit work (%d)\n", err);
+		return err;
+	}
+
+	/* wait for completion */
+	wait_args.id = get_syncpt_args.id;
+	wait_args.thresh = submit_args.fence;
+	wait_args.timeout = DRM_TEGRA_NO_TIMEOUT;
+	err = drmIoctl(fd, DRM_IOCTL_TEGRA_SYNCPT_WAIT, &wait_args);
+	if (err)
+		printf("Failed to wait for completion (%d)\n", err);
+
+	for (i = 0; i < 32; i++) {
+		for (j = 0; j < 199; j++) {
+			uint32_t offset = i * 256 + j;
+			if (outbuf[offset] != 0x00ff00ff) {
+				printf("Content mismatch at offset %u (%x != 0x00ff00ff)\n",
+				       offset, outbuf[offset]);
+				return -1;
+			}
+		}
+	}
+
+	printf("\nTest passed\n\n");
+
+	drm_tegra_close(tegra);
+	close(fd);
+
+	return 0;
+}
diff --git a/tests/tegra/vic.h b/tests/tegra/vic.h
new file mode 100644
index 000000000000..0bf08115fc65
--- /dev/null
+++ b/tests/tegra/vic.h
@@ -0,0 +1,426 @@
+/*
+ * Copyright © 2015 NVIDIA Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef VIC_H
+#define VIC_H
+
+#define VIC_UCLASS_INCR_SYNCPT					0x00
+#define VIC_UCLASS_METHOD_OFFSET				0x10
+#define VIC_UCLASS_METHOD_DATA					0x11
+
+#define NVA0B6_VIDEO_COMPOSITOR_EXECUTE				0x00000300
+#define NVA0B6_VIDEO_COMPOSITOR_SET_CONTROL_PARAMS		0x00000700
+#define NVA0B6_VIDEO_COMPOSITOR_SET_CONFIG_STRUCT_OFFSET	0x00000720
+#define NVA0B6_VIDEO_COMPOSITOR_SET_HIST_OFFSET			0x00000728
+#define NVA0B6_VIDEO_COMPOSITOR_SET_OUTPUT_SURFACE_LUMA_OFFSET	0x00000730
+
+typedef struct _SurfaceCache0Struct {
+	uint64_t DeNoise0            : 1;
+	uint64_t CadenceDetect0      : 1;
+	uint64_t MotionMap0          : 1;
+	uint64_t MedianFilter0       : 1;
+	uint64_t DeNoise1            : 1;
+	uint64_t CadenceDetect1      : 1;
+	uint64_t MotionMap1          : 1;
+	uint64_t MedianFilter1       : 1;
+	uint64_t DeNoise2            : 1;
+	uint64_t CadenceDetect2      : 1;
+	uint64_t MotionMap2          : 1;
+	uint64_t MedianFilter2       : 1;
+	uint64_t DeNoise3            : 1;
+	uint64_t CadenceDetect3      : 1;
+	uint64_t MotionMap3          : 1;
+	uint64_t MedianFilter3       : 1;
+	uint64_t DeNoise4            : 1;
+	uint64_t CadenceDetect4      : 1;
+	uint64_t MotionMap4          : 1;
+	uint64_t MedianFilter4       : 1;
+	uint64_t IsEven0             : 1;
+	uint64_t IsEven1             : 1;
+	uint64_t IsEven2             : 1;
+	uint64_t IsEven3             : 1;
+	uint64_t IsEven4             : 1;
+	uint64_t MMapCombine0        : 1;
+	uint64_t MMapCombine1        : 1;
+	uint64_t MMapCombine2        : 1;
+	uint64_t MMapCombine3        : 1;
+	uint64_t MMapCombine4        : 1;
+	uint64_t reserved0           : 2;
+	uint64_t PixelFormat0        : 7;
+	uint64_t reserved1           : 1;
+	uint64_t PixelFormat1        : 7;
+	uint64_t reserved2           : 1;
+	uint64_t PixelFormat2        : 7;
+	uint64_t reserved3           : 1;
+	uint64_t PixelFormat3        : 7;
+	uint64_t reserved4           : 1;
+	uint64_t PixelFormat4        : 7;
+	uint64_t reserved5           : 1;
+	uint64_t reserved6           : 24;
+	uint64_t PPMotion0           : 1;
+	uint64_t PPMotion1           : 1;
+	uint64_t PPMotion2           : 1;
+	uint64_t PPMotion3           : 1;
+	uint64_t PPMotion4           : 1;
+	uint64_t reserved7           : 3;
+	uint64_t ChromaEven0         : 1;
+	uint64_t ChromaEven1         : 1;
+	uint64_t ChromaEven2         : 1;
+	uint64_t ChromaEven3         : 1;
+	uint64_t ChromaEven4         : 1;
+	uint64_t reserved8           : 3;
+	uint64_t AdvancedDenoise0    : 1;
+	uint64_t AdvancedDenoise1    : 1;
+	uint64_t AdvancedDenoise2    : 1;
+	uint64_t AdvancedDenoise3    : 1;
+	uint64_t AdvancedDenoise4    : 1;
+	uint64_t reserved9           : 3;
+	uint64_t reserved10          : 8;
+} SurfaceCache0Struct;
+
+
+typedef struct _SurfaceList0Struct {
+	uint64_t ClearRectMask0      : 8;
+	uint64_t ClearRectMask1      : 8;
+	uint64_t ClearRectMask2      : 8;
+	uint64_t ClearRectMask3      : 8;
+	uint64_t ClearRectMask4      : 8;
+	uint64_t reserved0           : 22;
+	uint64_t OutputFlipX         : 1;
+	uint64_t OutputFlipY         : 1;
+	uint64_t TargetRectLeft      : 14;
+	uint64_t reserved1           : 2;
+	uint64_t TargetRectRight     : 14;
+	uint64_t reserved2           : 2;
+	uint64_t TargetRectTop       : 14;
+	uint64_t reserved3           : 2;
+	uint64_t TargetRectBottom    : 14;
+	uint64_t reserved4           : 2;
+} SurfaceList0Struct;
+
+
+typedef struct _SurfaceListClearRectStruct {
+	uint64_t ClearRect0Left      : 14;
+	uint64_t reserved0           : 2;
+	uint64_t ClearRect0Right     : 14;
+	uint64_t reserved1           : 2;
+	uint64_t ClearRect0Top       : 14;
+	uint64_t reserved2           : 2;
+	uint64_t ClearRect0Bottom    : 14;
+	uint64_t reserved3           : 2;
+	uint64_t ClearRect1Left      : 14;
+	uint64_t reserved4           : 2;
+	uint64_t ClearRect1Right     : 14;
+	uint64_t reserved5           : 2;
+	uint64_t ClearRect1Top       : 14;
+	uint64_t reserved6           : 2;
+	uint64_t ClearRect1Bottom    : 14;
+	uint64_t reserved7           : 2;
+} SurfaceListClearRectStruct;
+
+
+typedef struct _SurfaceListSurfaceStruct {
+	uint64_t Enable              : 1;
+	uint64_t FrameFormat         : 4;
+	uint64_t PixelFormat         : 7;
+	uint64_t reserved0           : 2;
+	uint64_t ChromaLocHoriz      : 2;
+	uint64_t ChromaLocVert       : 2;
+	uint64_t Panoramic           : 12;
+	uint64_t reserved1           : 4;
+	uint64_t SurfaceWidth        : 14;
+	uint64_t reserved2           : 1;
+	uint64_t SurfaceHeight       : 14;
+	uint64_t reserved3           : 1;
+	uint64_t LumaWidth           : 14;
+	uint64_t reserved4           : 1;
+	uint64_t LumaHeight          : 14;
+	uint64_t reserved5           : 1;
+	uint64_t ChromaWidth         : 14;
+	uint64_t reserved6           : 1;
+	uint64_t ChromaHeight        : 14;
+	uint64_t reserved7           : 1;
+	uint64_t CacheWidth          : 3;
+	uint64_t reserved8           : 1;
+	uint64_t FilterLengthY       : 2;
+	uint64_t FilterLengthX       : 2;
+	uint64_t DetailFltClamp      : 6;
+	uint64_t reserved9           : 2;
+	uint64_t LightLevel          : 4;
+	uint64_t reserved10          : 4;
+	uint64_t reserved11          : 8;
+	uint64_t reserved12          : 32;
+	uint64_t BlkKind             : 4;
+	uint64_t DestRectLeft        : 14;
+	uint64_t reserved13          : 1;
+	uint64_t DestRectRight       : 14;
+	uint64_t reserved14          : 1;
+	uint64_t DestRectTop         : 14;
+	uint64_t reserved15          : 1;
+	uint64_t DestRectBottom      : 14;
+	uint64_t reserved16          : 1;
+	uint64_t BlkHeight           : 4;
+	uint64_t SourceRectLeft      : 30;
+	uint64_t reserved17          : 2;
+	uint64_t SourceRectRight     : 30;
+	uint64_t reserved18          : 2;
+	uint64_t SourceRectTop       : 30;
+	uint64_t reserved19          : 2;
+	uint64_t SourceRectBottom    : 30;
+	uint64_t reserved20          : 2;
+} SurfaceListSurfaceStruct;
+
+
+typedef struct _ColorConversionLumaAlphaStruct {
+	uint64_t l0                  : 20;
+	uint64_t l1                  : 20;
+	uint64_t l2                  : 20;
+	uint64_t r_shift             : 4;
+	uint64_t l3                  : 20;
+	uint64_t PlanarAlpha         : 10;
+	uint64_t ConstantAlpha       : 1;
+	uint64_t ClipEnabled         : 1;
+	uint64_t LumaKeyLower        : 10;
+	uint64_t reserved6           : 3;
+	uint64_t StereoInterleave    : 3;
+	uint64_t LumaKeyUpper        : 10;
+	uint64_t reserved7           : 2;
+	uint64_t reserved8           : 1;
+	uint64_t LumaKeyEnabled      : 1;
+	uint64_t reserved9           : 2;
+} ColorConversionLumaAlphaStruct;
+
+
+typedef struct _ColorConversionMatrixStruct {
+	uint64_t c00                 : 20;
+	uint64_t c10                 : 20;
+	uint64_t c20                 : 20;
+	uint64_t r_shift             : 4;
+	uint64_t c01                 : 20;
+	uint64_t c11                 : 20;
+	uint64_t c21                 : 20;
+	uint64_t reserved0           : 4;
+	uint64_t c02                 : 20;
+	uint64_t c12                 : 20;
+	uint64_t c22                 : 20;
+	uint64_t reserved1           : 4;
+	uint64_t c03                 : 20;
+	uint64_t c13                 : 20;
+	uint64_t c23                 : 20;
+	uint64_t reserved2           : 4;
+} ColorConversionMatrixStruct;
+
+
+typedef struct _ColorConversionClampStruct {
+	uint64_t low                 : 10;
+	uint64_t reserved0           : 6;
+	uint64_t high                : 10;
+	uint64_t reserved1           : 6;
+	uint64_t reserved2           : 32;
+	uint64_t reserved3           : 32;
+	uint64_t reserved4           : 32;
+} ColorConversionClampStruct;
+
+
+typedef struct _Blending0Struct {
+	uint64_t PixelFormat         : 7;
+	uint64_t reserved0           : 1;
+	uint64_t AlphaFillMode       : 3;
+	uint64_t AlphaFillSlot       : 3;
+	uint64_t BackgroundAlpha     : 10;
+	uint64_t BackgroundR         : 10;
+	uint64_t BackgroundG         : 10;
+	uint64_t BackgroundB         : 10;
+	uint64_t ChromaLocHoriz      : 2;
+	uint64_t ChromaLocVert       : 2;
+	uint64_t reserved1           : 6;
+	uint64_t LumaWidth           : 14;
+	uint64_t reserved2           : 2;
+	uint64_t LumaHeight          : 14;
+	uint64_t reserved3           : 2;
+	uint64_t ChromaWidth         : 14;
+	uint64_t reserved4           : 2;
+	uint64_t ChromaHeight        : 14;
+	uint64_t reserved5           : 2;
+	uint64_t TargetRectLeft      : 14;
+	uint64_t reserved6           : 2;
+	uint64_t TargetRectRight     : 14;
+	uint64_t reserved7           : 2;
+	uint64_t TargetRectTop       : 14;
+	uint64_t reserved8           : 2;
+	uint64_t TargetRectBottom    : 14;
+	uint64_t reserved9           : 2;
+	uint64_t SurfaceWidth        : 14;
+	uint64_t reserved10          : 2;
+	uint64_t SurfaceHeight       : 14;
+	uint64_t reserved11          : 2;
+	uint64_t BlkKind             : 4;
+	uint64_t BlkHeight           : 4;
+	uint64_t OutputFlipX         : 1;
+	uint64_t OutputFlipY         : 1;
+	uint64_t OutputTranspose     : 1;
+	uint64_t reserved12          : 21;
+} Blending0Struct;
+
+
+typedef struct _BlendingSurfaceStruct {
+	uint64_t AlphaK1             : 10;
+	uint64_t reserved0           : 6;
+	uint64_t AlphaK2             : 10;
+	uint64_t reserved1           : 6;
+	uint64_t SrcFactCMatchSelect : 3;
+	uint64_t reserved2           : 1;
+	uint64_t DstFactCMatchSelect : 3;
+	uint64_t reserved3           : 1;
+	uint64_t SrcFactAMatchSelect : 3;
+	uint64_t reserved4           : 1;
+	uint64_t DstFactAMatchSelect : 3;
+	uint64_t reserved5           : 1;
+	uint64_t reserved6           : 4;
+	uint64_t reserved7           : 4;
+	uint64_t reserved8           : 4;
+	uint64_t reserved9           : 4;
+	uint64_t reserved10          : 2;
+	uint64_t OverrideR           : 10;
+	uint64_t OverrideG           : 10;
+	uint64_t OverrideB           : 10;
+	uint64_t OverrideA           : 10;
+	uint64_t reserved11          : 2;
+	uint64_t UseOverrideR        : 1;
+	uint64_t UseOverrideG        : 1;
+	uint64_t UseOverrideB        : 1;
+	uint64_t UseOverrideA        : 1;
+	uint64_t MaskR               : 1;
+	uint64_t MaskG               : 1;
+	uint64_t MaskB               : 1;
+	uint64_t MaskA               : 1;
+	uint64_t reserved12          : 12;
+} BlendingSurfaceStruct;
+
+
+typedef struct _FetchControl0Struct {
+	uint64_t TargetRectLeft      : 14;
+	uint64_t reserved0           : 2;
+	uint64_t TargetRectRight     : 14;
+	uint64_t reserved1           : 2;
+	uint64_t TargetRectTop       : 14;
+	uint64_t reserved2           : 2;
+	uint64_t TargetRectBottom    : 14;
+	uint64_t reserved3           : 2;
+	uint64_t Enable0             : 8;
+	uint64_t Enable1             : 8;
+	uint64_t Enable2             : 8;
+	uint64_t Enable3             : 8;
+	uint64_t Enable4             : 8;
+	uint64_t DownsampleHoriz     : 11;
+	uint64_t reserved4           : 1;
+	uint64_t DownsampleVert      : 11;
+	uint64_t reserved5           : 1;
+	uint64_t FilterNoise0        : 10;
+	uint64_t FilterDetail0       : 10;
+	uint64_t FilterNoise1        : 10;
+	uint64_t reserved6           : 2;
+	uint64_t FilterDetail1       : 10;
+	uint64_t FilterNoise2        : 10;
+	uint64_t FilterDetail2       : 10;
+	uint64_t reserved7           : 2;
+	uint64_t FilterNoise3        : 10;
+	uint64_t FilterDetail3       : 10;
+	uint64_t FilterNoise4        : 10;
+	uint64_t reserved8           : 2;
+	uint64_t FilterDetail4       : 10;
+	uint64_t reserved9           : 22;
+	uint64_t ChromaNoise0        : 10;
+	uint64_t ChromaDetail0       : 10;
+	uint64_t ChromaNoise1        : 10;
+	uint64_t reserved10          : 2;
+	uint64_t ChromaDetail1       : 10;
+	uint64_t ChromaNoise2        : 10;
+	uint64_t ChromaDetail2       : 10;
+	uint64_t reserved11          : 2;
+	uint64_t ChromaNoise3        : 10;
+	uint64_t ChromaDetail3       : 10;
+	uint64_t ChromaNoise4        : 10;
+	uint64_t reserved12          : 2;
+	uint64_t ChromaDetail4       : 10;
+	uint64_t reserved13          : 22;
+	uint64_t Mode0               : 4;
+	uint64_t AccumWeight0        : 3;
+	uint64_t Iir0                : 11;
+	uint64_t reserved14          : 2;
+	uint64_t Mode1               : 4;
+	uint64_t AccumWeight1        : 3;
+	uint64_t Iir1                : 11;
+	uint64_t reserved15          : 2;
+	uint64_t Mode2               : 4;
+	uint64_t AccumWeight2        : 3;
+	uint64_t Iir2                : 11;
+	uint64_t reserved16          : 6;
+	uint64_t Mode3               : 4;
+	uint64_t AccumWeight3        : 3;
+	uint64_t Iir3                : 11;
+	uint64_t reserved17          : 2;
+	uint64_t Mode4               : 4;
+	uint64_t AccumWeight4        : 3;
+	uint64_t Iir4                : 11;
+	uint64_t reserved18          : 8;
+	uint64_t OutputFlipX         : 1;
+	uint64_t OutputFlipY         : 1;
+	uint64_t reserved19          : 10;
+	uint64_t reserved20          : 6;
+} FetchControl0Struct;
+
+
+typedef struct _FetchControlCoeffStruct {
+	uint64_t f00                 : 10;
+	uint64_t f10                 : 10;
+	uint64_t f20                 : 10;
+	uint64_t reserved0           : 2;
+	uint64_t f01                 : 10;
+	uint64_t f11                 : 10;
+	uint64_t f21                 : 10;
+	uint64_t reserved1           : 2;
+	uint64_t f02                 : 10;
+	uint64_t f12                 : 10;
+	uint64_t f22                 : 10;
+	uint64_t reserved2           : 2;
+	uint64_t f03                 : 10;
+	uint64_t f13                 : 10;
+	uint64_t f23                 : 10;
+	uint64_t reserved3           : 2;
+} FetchControlCoeffStruct;
+
+typedef struct _ConfigStruct {
+	SurfaceCache0Struct                  surfaceCache0Struct;
+	SurfaceList0Struct                   surfaceList0Struct;
+	SurfaceListClearRectStruct           surfaceListClearRectStruct[4];
+	SurfaceListSurfaceStruct             surfaceListSurfaceStruct[5];
+	ColorConversionLumaAlphaStruct       colorConversionLumaAlphaStruct[5];
+	ColorConversionMatrixStruct          colorConversionMatrixStruct[5];
+	ColorConversionClampStruct           colorConversionClampStruct[5];
+	Blending0Struct                      blending0Struct;
+	BlendingSurfaceStruct                blendingSurfaceStruct[5];
+	FetchControl0Struct                  fetchControl0Struct;
+	FetchControlCoeffStruct              fetchControlCoeffStruct[520];
+} ConfigStruct;
+
+#endif
